VHDL 1076.1: Analog and Mixed-Signal Extensions to VHDL

  • Ernst Christen
  • Kenneth Bakalar
Part of the Current Issues in Electronic Modeling book series (CIEM, volume 10)


VHDL 1076.1 is an extension to the well-established VHDL 1076 language to support the description and simulation of continuous and mixed continuous/discrete systems. We provide an overview of the extended language.


Break Statement Extended Language Tolerance Group Simultaneous Statement Simple Nature 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media Dordrecht 1997

Authors and Affiliations

  • Ernst Christen
    • 1
  • Kenneth Bakalar
    • 2
  1. 1.Analogy, Inc.BeavertonUSA
  2. 2.Compass Design AutomationColumbiaUSA

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