Abstract
We present in this chapter a modeling style and control synthesis technique for system-level specifications that are better described as a set of concurrent descriptions, their synchronizations and complex constraints. For these types of specifications, conventional synthesis tools will not be able to enforce design constraints because these tools are targeted to sequential components with simple design constraints.
In order to schedule operations satisfying the constraints of system-level specifications, we propose a synthesis tool called Thalia that considers the degrees of freedom introduced by the concurrent models and by the system’s environment.
The synthesis procedure is subdivided into the following steps: we first model the specification in an algebraic formalism called control-flow expressions, that considers most of the language constructs used to model systems reacting to their environment, i.e. sequential, alternative, concurrent, iterative, and exception handling behaviors. Such constructs are found in languages such as C, Verilog HDL, VHDL, Esterel and StateCharts.
Then, we convert this model and a suitable representation for the environment into a finite-state machine, where the system is analyzed, and design constraints such as timing, resource and synchronization are incorporated. The operations in this representation are scheduled using a 0–1 Integer Linear Programming solver implemented with Binary Decision Diagrams.
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Coelho, C.N., De Micheli, G. (1997). Modeling And Synthesis of Synchronous System-Level Specifications. In: Bergé, JM., Levia, O., Rouillard, J. (eds) Models in System Design. Current Issues in Electronic Modeling, vol 9. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-6295-5_1
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DOI: https://doi.org/10.1007/978-1-4615-6295-5_1
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