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Chemical Vapor Deposition of Ferroelectric Thin Films

Chapter
Part of the Electronic Materials: Science and Technology book series (EMST, volume 3)

Abstract

For much of its recent history, advances in integrated circuit (IC) technology have been largely the result of a rapid and steady increase in the on-chip circuit element density. This trend is most apparent in the case of volatile digital memories [e.g., dynamic-random-access memory (DRAM)], where the current memory densities are approaching 1 Gbit. This has lead dramatic strides in circuit functionality, compactness, energy efficiency, and reliability. This course to higher integration densities has been driven by both technological and economic forces. However, the cost of this process has been the dramatic decrease in component dimensions and substantial increase in processing complexity in ultra-large-scale-integration (ULSI) of circuits. The performance specifications of ULSI have begun to challenge the ability of conventional IC materials at a fundamental properties level. Consequently, device manufacturers have been forces to consider the integration of “novel” materials into future-generation ICs [1, 2, 3]. In DRAM, for example, as the allowed cell area for the storage-node capacitor continues to decrease, the required storage charge also decreases but at a proportionally slower rate. A current strategy to overcome this problem is to replace the conventional silicon-oxide-nitride-oxide (ONO) layered dielectric with a material with significantly higher dielectric permittivity. For this application, the development of thin-film perovskite-structured oxide dielectrics such as (BaxSr1-x)TiO3 (BST) has received considerable attention since these materials typically exhibit dielectric permittivities two orders of magnitude higher than that of conventional ONO dielectrics [1, 2, 3]. By incorporating such high-dielectric-constant materials into storage-node capacitor structures, the capacitor area and the number and complexity of the process step required to form it can be decreased [4]. In addition, simple planar- or bumped-capacitor structures can be used as opposed to the complex. ULSI-scale geometries requisite with ONO dielectrics to provide the required capacitor area (thus capacitance) [5].

Keywords

Deposition Chamber Metalorganic Chemical Vapor Deposition Ferroelectric Thin Film Ferroelectric Hysteresis Loop Delivery Line 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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© Springer Science+Business Media New York 1997

Authors and Affiliations

  1. 1.Materials Science DivisionArgonne National LaboratoryArgonne IllinoisUSA

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