Abstract
Adiabatic design is an attractive approach to reducing energy consumption in VLSI circuits after exhausting the potential of conventional energy-saving techniques. Despite the plethora of adiabatic logic architectures that have been proposed in recent years, several practical considerations in the design of nontrivial adiabatic circuits remain largely unexplored. Moreover, it is still unclear whether adiabatic circuits of significant size and complexity can achieve substantial savings in energy dissipation over corresponding conventional designs.
We recently designed several low-power arithmetic units using a dual-rail adiabatic logic design style. We also designed static CMOS versions of these units and compared their energy dissipation with their corresponding adiabatic designs. In this paper we describe our implementations, discuss architecture and logic-level issues related to our adiabatic designs, and present the findings of our empirical comparison. Our results suggest that adiabatic logic can be used for the implementation of relatively complex VLSI circuits that dissipate significantly less energy than their corresponding CMOS designs.
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References
T. H. Cormen, C. E. Leiserson, and R. L. Rivest. Introduction to Algorithms. McGraw-Hill, MIT Press, 1990.
J. Denker, S. Avery, A. Dickinson, A. Kramer, and T. Wik. “Adiabatic computing with the 2N–2N2D logic family,” in 1994 International Workshop on Low Power Design, April 1994.
A. Dickinson and J. Denker. “Adiabatic dynamic logic,” in 1994 IEEE Custom Integrated Circuits Conference, May 1994.
R. Hinman and M. Schlecht. “Recovered energy logic: A highly efficient alternative to today’s logic circuits,” in IEEE Power Electronics Specialists Conference Record, pages 417–26, 1993.
T. Indermaur and M. Horowitz. “Evaluation of charge recovering circuits and adiabatic switching for low power,” in 1994 IEEE Symposium on Low Power Electronics, October 1994.
A. Kramer, J. Denker, B. Flower, and J. Mulroney. “2nd order adiabatic computation with 2N–2P and 2N–2N2P logic circuits,” in 1995 International Symposium on Low Power Design, April 1995.
N. Weste and K. Eshraghian. CMOS VLSI Design. Addison-Wesley: Reading, MA, 1985.
S. Younis. Asymptotically Zero Energy Computing Using Split-Level Charge Recovery Logic. PhD thesis, Massachusetts Institute of Technology, June 1994. Available as MIT/AITR-1500.
S. Younis and T. Knight. “Practical implementation of charge recovering asymptotically zero-power CMOS,” in Research in Integrated Systems: Proceedings of the 1993 Symposium, March 1993.
S. Younis and T. Knight. “Asymptotically zero energy split-level charge recovery logic,” in 1994 International Workshop on Low Power Design, April 1994.
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© 1997 Springer Science+Business Media New York
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Knapp, M.C., Kindlmann, P.J., Papaefthymiou, M.C. (1997). Design and Evaluation of Adiabatic Arithmetic Units. In: Becerra, J.J., Friedman, E.G. (eds) Analog Design Issues in Digital VLSI Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-6101-9_7
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DOI: https://doi.org/10.1007/978-1-4615-6101-9_7
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