Concurrency and Behavioral Modeling

Abstract

In Chapter 1 we briefly discussed the main design styles supported by VHDL and introduced concepts of concurrent and sequential statements and their basic use in VHDL descriptions. The concept of concurrency is the essential one to VHDL and it differentiates VHDL from high-level programming languages. This concept is useful for both VHDL synthesis and simulation. Also, it helps to describe both combinational and registered logic. Concurrent statements are specified exclusively in one place in VHDL, between the begin and end statements of an architecture declaration. All statements described in this part of architecture declaration are considered to be parallel in the execution and of equal priority. Besides signal assignment statements which are used to describe parallel execution, processes can be used with the same purpose. There is no order dependency of concurrent statements, and, therefore, we can specify them in any order. The key element in description of concurrent executions is the concept of signals, as the mechanism to communicate between components and between processes. Various assignment statements can be considered as connections between different types of objects, just as it is described by netlists in schematic diagrams.