Abstract
In this chapter we describe the enhancement of the ATPG-based framework by local BDD-based techniques. This enhancement involves two ideas. First, we generalize the inductive algorithm of Section 4.3 to identify equivalent flip-flop pairs and sequentially equivalent internal signal pairs. Secondly, we incorporate a heuristic called partial justification to handle larger designs using local BDDs. The approach is much less vulnerable to a memory explosion than the traditional symbolic FSM traversal and is, therefore, suitable for real-life designs. A prototype tool called AQUILA is implemented to demonstrate the efficiency and advantage of this method.
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© 1998 Springer Science+Business Media New York
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Huang, SY., Cheng, KT. (1998). AQUILA: A Local BDD-based Equivalence Verifier. In: Formal Equivalence Checking and Design Debugging. Frontiers in Electronic Testing, vol 12. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-5693-0_5
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DOI: https://doi.org/10.1007/978-1-4615-5693-0_5
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-7606-4
Online ISBN: 978-1-4615-5693-0
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