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Low Power Design in Deep Submicron Electronics pp 179–201Cite as

Advanced Power Estimation Techniques

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Part of the book series: NATO ASI Series ((ASIE,volume 337))

Abstract

This chapter describes a methodology and techniques for power estimation and analysis at behavioral, register-transfer and gate levels of design abstraction. The major components of the proposed methodology are survey sampling techniques, probabilistic compaction techniques, RTL co-simulation engine, power macro-modeling, and high-level power estimation.

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References

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Author information

Authors and Affiliations

  1. Department of Electrical Engineering — Systems, University of Southern California, Los Angeles, CA, 90089, USA

    Massoud Pedram

Authors
  1. Massoud Pedram
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Editor information

Editors and Affiliations

  1. Carl von Ossietzky Universität Oldenburg, and OFFIS, Oldenburg, Germany

    Wolfgang Nebel

  2. Laboratoire TIMA, Grenoble, France

    Jean Mermet (Directeur de recherches au CNRS) (Directeur de recherches au CNRS)

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© 1997 Springer Science+Business Media Dordrecht

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Pedram, M. (1997). Advanced Power Estimation Techniques. In: Nebel, W., Mermet, J. (eds) Low Power Design in Deep Submicron Electronics. NATO ASI Series, vol 337. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-5685-5_7

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  • DOI: https://doi.org/10.1007/978-1-4615-5685-5_7

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-7923-8103-7

  • Online ISBN: 978-1-4615-5685-5

  • eBook Packages: Springer Book Archive

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