Abstract
This chapter focuses on techniques for synthesizing delay fault testable circuits. The presented techniques concentrate on transition or path delay faults. Robust tests for these faults can guarantee their detection independent of signal delays outside the target path. Therefore, it would be ideal if all faults could be tested with robust tests. However, in most designs a significant fraction of delay faults is not robustly testable. Unlike in stuck-at fault testing, redundancy removal techniques cannot be used to eliminate untestable delay faults. There are two reasons for this: (a) An untestable path delay fault is not necessarily redundant and thus it may not be removed. (2) Even if a path is redundant, the signals involved in the path are usually shared by many paths. Removing a path from a circuit would then, require duplication of the logic and thus, result in an area increase. A number of synthesis techniques tuned to obtain circuits with improved robust delay fault testability have been developed [33, 40, 89, 118, 127, 130]. These methods either start from the functional specification of the circuit and synthesize it such that all faults are robustly testable or they identify the robustly untestable faults in the given implementation and modify it to achieve complete robust delay fault testability. Synthesis of robust delay fault testable designs can result in a large area/performance overhead and or additional primary inputs. In case of the path delay faults, more area efficient delay testable designs can be obtained if in addition to robustly testable faults the synthesized designs also allowed to contain validatable non-robustly testable faults as well as primitive faults of cardinality higher than 1. Defects causing all these faults can be detected without regard to circuit delays. However, unless the test set for such a design is obtained during the synthesis process, generating tests for validatable non-robustly testable and primitive faults of cardinality higher than 1 is a complicated task.
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© 1998 Springer Science+Business Media New York
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Krstić, A., Cheng, KT. (1998). Synthesis for Delay Fault Testability. In: Delay Fault Testing for VLSI Circuits. Frontiers in Electronic Testing, vol 14. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-5597-1_9
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DOI: https://doi.org/10.1007/978-1-4615-5597-1_9
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-7561-6
Online ISBN: 978-1-4615-5597-1
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