Abstract
Estimation of cycle time is fairly straightforward for an existing CPU design where low-level tools, called timing estimators or verifiers, can simulate path delay times and identify critical paths from the netlist. However estimation of clock cycle time for a design in progress, or an alternative for which no implementation exists, is much more difficult. In practice, designers determine a target cycle time and estimate the actual cycle time by examining what they believe to be the critical paths in the design. So, designers rely heavily on their experience and then do whatever is needed to try to achieve their clock cycle target.
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Geuskens, B., Rose, K. (1998). Cycle Time Estimation Model. In: Modeling Microprocessor Performance. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-5561-2_7
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DOI: https://doi.org/10.1007/978-1-4615-5561-2_7
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