Polyphase-Coefficient Structures for 2-D Decimation Filters

Abstract

As mentioned in previous chapters, the implementation of 2-D SC filtering functions using multirate processing techniques is motivated by the need to reduce both the processing speed and complexity of the implementing circuits. This, of course, depends on the type of application and image standard (e.g. NTSC and PAL). For example, we can observe in Table 4.1 that the multirate SC implementation of a chrominance separation 2-D filter for NTSC systems requires only one fourth of the size of the delay-line (DL) memory block needed in a traditional (non-multirate) design, besides eliminating 42 clock signals and reducing the clock rate from 14 MHz to 3.5 MHz. Similar gains are obtained for the case of the picture enhancement 2-D filter also given in Table 4.1.