The main contribution of this book has been to develop the techniques and the methodology for effective power reduction during logic synthesis. A necessary requirement for effective power optimization is a power model that can effectively be used during logic synthesis. This book also presented a power model which was proven to be highly accurate for minimizing the zero-delay model power cost. POSE (Power Optimization and Synthesis Environment) has been developed by implementing the techniques described in this book. POSE provides the necessary steps for transforming the Boolean representation of a design into a technology mapped circuit. POSE also provides the necessary power estimation techniques to guide the power optimization procedures.
KeywordsPower Consumption Power Optimization Power Model Logic Synthesis Boolean Representation
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