Abstract
This section examines the applications of the Dynamic Model in formally reasoning about VHDL programs. In particular, the model is used to validate two transformation rules (Sections 9.2 and 9.3) and to derive conditions under which no transaction preemption occurs (Section 9.4). The results derived herein are aimed at CAD tool optimization.
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© 1999 Springer Science+Business Media New York
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Umamageswaran, K., Pandey, S.L., Wilsey, P.A. (1999). Applications of the Dynamic Model. In: Formal Semantics and Proof Techniques for Optimizing VHDL Models. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-5123-2_9
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DOI: https://doi.org/10.1007/978-1-4615-5123-2_9
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-7331-5
Online ISBN: 978-1-4615-5123-2
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