Abstract
An experimental implementation of the ΣΔ modulator architecture described in Chapter 5 has been integrated in a 0.8-μm CMOS process with poly-to-metal capacitors and operates from a nominal supply voltage of 1.8 V. While the entire analog signal path and the clock circuits for this modulator have been integrated on a single chip, much of the digital postprocessing, including the error cancellation networks and the digital decimation filter, has been implemented in software. The setup used to test the experimental prototype is described in Appendix D.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
K. L. Lee and R. Meyer, “Low-distortion switched-capacitor filter design techniques,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 1103–1112, December 1985.
W. Black, D. Allstot, and R. Reed, “A high performance low power CMOS channel filter,” IEEEJ. Solid-State Circuits, vol. SC-15, pp. 929–938, Dec. 1980.
B. Ahuja, “An improved frequency compensation technique for CMOS operational amplifiers,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 629–633, Dec. 1983.
D. Senderowicz, et al., “Low voltage double sampled ΣΔ converters,” IEEE J. Solid-State Circuits, vol. SC-32, pp. 1907–1919, Dec. 1997.
J. Candy and G. Temes, “Oversampling methods for A/D and D/A conversion,” in Oversampling Delta-Sigma Data Converters, pp. 1–29, New York: IEEE Press, 1992.
L. Williams, and B. A. Wooley, “MIDAS-a functional simulator for mixed digital and analog sampled data systems,” Proc. 1992 IEEE Int. Symp. Circuits Syst., pp. 2148–2151, May 1992.
S. Rabii, L. Williams, B. Boser, and B. A. Wooley, MIDAS User Guide Version 3.1, Stanford University, Stanford, CA, 1997.
E. J. van der Zwan and E. C. Dijkmans, “A 0.2mW CMOS ΣΔ modulator for speech coding with 80dB dynamic range,” 1SSCC Digest of Tech. Papers, pp. 232–233, February 1996.
S. Kiriaki, “A 0.25mW sigma-delta modulator for voice-band applications,” Symp. on VLSI Circuits Digest of Tech. Papers, pp. 35–36, 1995.
J. Grilo, E. MacRobbie, R. Halim, and G. Temes, “A 1.8V 94dB dynamic range ΣΔ modulator for voice applications,” ISSCC Digest of Tech. Papers, pp. 232–233, February 1996.
K. Kusumoto, A. Matsuzawa, and K. Murata, “A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC“ IEEE J. Solid-State Circuits, vol. SC-28, pp. 1200–1206, December 1993.
M. Yotsuyanagi, H. Hasegawa, M. Yamaguchi, M. Ishida, and K. Sone, “A 2V 10b 20MSample/s mixed-mode subranging CMOS A/D converter,” ISSCC Digest of Tech. Papers, pp. 282–283, February 1995.
T. B. Cho and P. R. Gray, “A 10 b, 20 Msample/s, 35 mW pipeline A/D converter,” IEEE J. Solid-State Circuits, vol. SC-30, pp. 166–172, March 1995.
A. G. W. Venes and R. J. van de Plassche, “An 80MHz 80mW 8b CMOS folding A/D converter with distributed T/H preprocessing,” ISSCC Digest of Tech. Papers, pp. 318–319, February 1996.
L. Williams and B. A. Wooley, “A third-order sigma-delta modulator with extended dynamic range,” IEEE J. Solid-State Circuits, vol. SC-29, pp. 193–202, March 1994.
B. P. Brandt and B. A. Wooley, “A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/D conversion,” 1EEEJ. Solid-State Circuits, vol. SC-26, pp. 1746–1756, December 1991.
G. Yin, F. Stubbe, and W. Sansen, “A 16-b 320-kHz CMOS A/D converter using two-stage third-order ΣΔ noise shaping,” IEEE J. Solid-State Circuits, vol. SC-28, pp. 640–647, June 1993.
P. C. Yu and H.-S. Lee, “A 2.5V 12b 5MSample/s pipelined CMOS ADC,” ISSCC Digest of Tech. Papers, pp. 314–315, February 1996.
M. P. Flynn and D. J. Allstot, “CMOS folding ADCs with current-mode interpolation,” ISSCC Digest of Tech. Papers, pp. 374–375, February 1995.
Y. Matsuya and J. Yamada, “1 V power supply, low power consumption A/D conversion technique with swing-suppression noise shaping,” IEEE J. Solid-State Circuits, vol. SC-29, pp. 1524–1530, December 1994.
V. Peluso, M. Steyaert, and W. Sansen, “A 1.5-V 100μW ΔΣ modulator with 12-b dynamic range using the switched-opamp technique,” IEEE J. Solid-State Circuits, vol. SC-32, pp. 943–952, July 1997.
S.-U. Kwak, B.-S. Song, and K. Bacrania, “A 15-b 5-Msample/s low-spurious CMOS ADC,” IEEEJ. Solid-State Circuits, vol. SC-32, pp. 1866–1875, December 1997.
A. Marques, V. Peluso, M. Steyaert, and W. Sansen, “A 15-b resolution 2-MHz Nyquist rate ΔΣ ADC in a 1-m CMOS technology,” IEEE J. Solid-State Circuits, vol. SC-33, pp. 1065–1075, July 1998.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 1999 Springer Science+Business Media New York
About this chapter
Cite this chapter
Rabii, S., Wooley, B.A. (1999). Implementation of an Experimental Low-Voltage Modulator. In: The Design of Low-Voltage, Low-Power Sigma-Delta Modulators. The Kluwer International Series in Engineering and Computer Science, vol 483. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-5105-8_6
Download citation
DOI: https://doi.org/10.1007/978-1-4615-5105-8_6
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-7322-3
Online ISBN: 978-1-4615-5105-8
eBook Packages: Springer Book Archive