Abstract
Two factors, technology scaling and battery life in portable electronics, are accelerating the reduction in the supply voltage used for CMOS VLSI circuits beyond what might be expected from historical trends. While the scaling of transistor dimensions results in dramatic increases in both the speed and density of digital circuits, it also results in a corresponding increase in the electric fields within the device if the supply voltage is held constant. Breakdown considerations thus make it increasingly difficult to sustain the constant supply voltage that has characterized the past two decades of advances in CMOS technology. Moreover, lowering the supply voltage significantly reduces the energy consumed per operation in a digital system.
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References
R. Muller and T. Kamins, Device Electronics for Integrated Circuits, John Wiley & Sons, 1986.
B. A. Gieseke, et al., “A 600MHz superscalar RISC microprocessor with out-of-order execution,” ISSCC Digest of Tech. Papers, pp. 176–177, February 1997.
J. D. Meindl, “Low power microelectronics: retrospect and prospect,” Proceedings of the IEEE, vol. 83, no. 4, pp. 619–635, April 1995.
R. Dennard, F. Gaensslen, H. Yu, V. Rideout, E. Bassous, and A. LeBlanc, “Design of ion-implanted MOSFET’s with very small physical dimensions,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 256–267, October 1974.
G. Baccarani, M. Wordeman, and R. Dennard, “Generalized scaling theory and its application to 1/4 micron MOSFET design,” IEEE Trans. on Electron Devices, vol. ED-31, pp. 452–462, April 1984.
B. Davari, R. Dennard, and G. Shahidi, “CMOS scaling for high performance and low power — the next ten years,” Proceedings of the IEEE, vol. 83, pp. 595–606, April 1995.
K. W. Terrill, C. Hu, and P. K. Ko, “An analytical model for the channel electric field in MOSFETs with graded-drain structures,” IEEE Electron Device Letters, vol. EDL-5, no. 11, pp. 440–442, November 1984.
L. Su, et al., “A high-performance 0.08 μm CMOS,” Symp. on VLSI Technology Digest of Tech. Papers, pp. 12–13, 1996.
R. Gonzalez, B. Gordon, and M. Horowitz, “Supply and threshold voltage scaling for low power CMOS“ IEEE J. Solid-State Circuits, vol. SC-32, pp. 1210–1216, August 1997.
C. Hu, “Gate oxide scaling limits and projection,” IEEE IEDM Tech. Dig., pp. 319–322, 1996.
A. Abidi, “High frequency noise measurements on FET’s with small dimensions,” IEEE Trans. on Electron Devices, vol. ED-33, pp. 1801–1805, November 1986.
M. Pelgrom, A. Duinmaijer, and A. Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, vol. SC-24, pp. 1433–1439, October 1989.
D. Linden, Handbook of Batteries, McGraw-Hill, 1994.
Gates Energy Products, Rechargeable Batteries Applications Handbook, Butterworth-Heinemann, 1992.
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Rabii, S., Wooley, B.A. (1999). Trends Toward Low-Voltage Power Supplies. In: The Design of Low-Voltage, Low-Power Sigma-Delta Modulators. The Kluwer International Series in Engineering and Computer Science, vol 483. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-5105-8_2
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DOI: https://doi.org/10.1007/978-1-4615-5105-8_2
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