Interfacing to C Models Using VPI Routines
Interfacing C language models to Verilog simulations is a common and powerful application of the Programming Language Interface. The VPI simulation callback routines presented in the previous chapter make it easy to create this interface, and to synchronize activity with logic value changes and with simulation time. This chapter shows several ways in which a C model can be interfaced to a Verilog simulation using the VPI routine library (Chapter 13 presents using the TF library for interfacing to C models, and Chapter 18 shows how to use the ACC library to accomplish this same task).
KeywordsModel Interface Path Delay System Task Combinational Logic Simulation Time Step
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