Skip to main content

The Industry Standard Flash Memory Cell

  • Chapter

Abstract

This chapter gives a thorough overview of the Industry Standard Flash Memory Cell. More than 85% of today Flash memories rely on this concept. We will describe the basic structure of the floating gate device, and its operating conditions. We will highlight the main differences in the technology and process with respect to a standard CMOS process. Finally, a brief introduction on some of the more important yield and reliability issues will be given.

Flash, a-ah Savior of the Universe

—Queen, Flash Gordon Soundtrack, 1980

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   259.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   329.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   329.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Frohman-Bentchkowsky D. (1971) “Memory behavior in a floating-gate avalanche-injection MOS (FAMOS) structure”. Applied Physics Letters, 18, pp. 332–334.

    Article  Google Scholar 

  2. Frohman-Bentchkowsky D. (1974) “FAMOS — a new semiconductor charge storage device”. Solid-State Electronics, 17, p. 517.

    Article  Google Scholar 

  3. Guterman D.C., Rimawi I.H., Chiu T.L., Halvorson R.D. and McElroy D.J. (1979) “An electrically alterable nonvolatile memory cell using a floatinggate structure”. IEEE Trans. on Electron Devices, 26,4, pp. 576–586.

    Article  Google Scholar 

  4. Masuoka F., Asano M., Iwahashi H., Komuro T. and Tanaka S. (1984) “A new Flash E2PROM cell using triple polysilicon technology”. IEDM Tech. Dig., pp. 464-467.

    Google Scholar 

  5. Verma G. and Mielke N. (1988) “Reliability performance of ETOX based Flash memories”. Proc. IRPS, p. 158.

    Google Scholar 

  6. Bauer M. et al. (1995) “A multi-level 32Mb Flash memory”. ISSCC Conf. Proc., p. 132.

    Google Scholar 

  7. Hemink G.J., Tanaka T., Endoh T., Aritome S. and Shirota R. (1995) “Fast and accurate programming method for multi-level NAND EEPROMs”. Digest of VLSI Symposium on VLSI Technology, no. 10B-4, pp. 129–130.

    Google Scholar 

  8. Eitan B., Kazerounian R., Roy A., Crisenza G., Cappelletti P. and Modelli A. (1996) “Multilevel flash cells and their trade-offs”. IEDM Tech. Dig., pp. 169-172.

    Google Scholar 

  9. Rodjy N. (1992) “0.85μm double metal CMOS technology for 5 V Flash EPROM memories with sector erase”. 12 th Nonvolatile Semiconductor Memory Symposium, Monterey, California (USA).

    Google Scholar 

  10. Bergemontr A., Haggag H., Anderson L., Shacham E. and Woltsenholme G. (1993) “NOR virtual ground (NVG) — a new scaling concept for very high density FLASH EEPROM and its implementation in a 0.5μm process”. IEDM Tech. Dig., pp. 15-18.

    Google Scholar 

  11. Bergemont A., Chi M. and Haggag H. (1996) “Low voltage NVG: a new high performance 3V/5V Flash technology for portable computing and telecommunications applications”. IEEE Trans, on Electron Devices, 43,9, pp. 1510–1517.

    Article  Google Scholar 

  12. Kynett V.N., Baker A., Fandrich M., Hoekstra G., Jungroth O., Kreifels J. and Wells S. (1988) “An in-system reprogrammable 256 K CMOS flash memory”. ISSCC Conf. Proc., p. 132.

    Google Scholar 

  13. Pavan P., Bez R., Olivo P. and Zanoni E. (1997) “Flash memory cells — an overview”. Proc. of the IEEE, 85,8, pp. 1248–1271.

    Article  Google Scholar 

  14. Mori S., Yamaguchi Y., Sato M., Meguro H., Tsunoda H., Kamiya E., Yoshikawa K., Arai N. and Sakagami E. (1996) “Thickness scaling limitation factors of ONO interpoly dielectric for nonvolatile memory devices”. IEEE Trans. on Electron Devices, 43,1, pp. 47–53.

    Article  Google Scholar 

  15. Venkatesh B., Chung M., Govindachar S., Santurkar V., Bill C., Gutala R., Zhou D., Yu J., Van Busirik M., Kawamura S., Kurihara K., Kawashima H. and Watanabe H. (1996) “A 55 ns 0.35μm 5 V-only 16 M flash memory with deep-power-down”. ISSCC Conf. Proc., no. TP 2.7, pp. 44–45.

    Google Scholar 

  16. Wang S.T. (1979) “On the I–V characteristics of floating-gate MOS transistors”. IEEE Trans. on Electron Devices, 26,9, pp. 1292–1294.

    Article  Google Scholar 

  17. Wada M., Mimura S., Nihira H. and Iizuka H. (1980) “Limiting factors for programming EPROM of reduced dimensions”. IEDM Tech. Dig., pp. 38-41.

    Google Scholar 

  18. Kolodny A., Nieh S.T.K., Eitan B. and Shappir J. (1986) “Analysis and modeling of floating gate EEPROM cells”. IEEE Trans, on Electron Devices, 33,6, pp. 835–844.

    Article  Google Scholar 

  19. Prall K., Kinney W.I. and Marco J. (1987) “Characterization and suppression of drain coupling in submicrometer EPROM cells”. IEEE Trans. on Electron Devices, 34,12, p. 2463.

    Article  Google Scholar 

  20. Wong M., Liu D.K.-Y. and Huang S.S.-W. (1992) “Analysis of the subthreshold slope and the linear transconductance techniques for the extraction of the capacitive coupling coefficients of floating-gate devices”. IEEE Electron Device Letters, 13,11, pp. 566–568.

    Article  Google Scholar 

  21. Choi W.L. and Kim D.M. (1994) “A new technique for measuring coupling coefficients and 3-D capacitance characterization of floating gate devices”. IEEE Trans. on Electron Devices, 41,12, pp. 2337–2342.

    Article  Google Scholar 

  22. Bez R., Camerlenghi E., Cantarelli D., Ravazzi L. and Crisenza G. (1990) “A novel method for the experimental determination of the coupling ratios in submicron EPROM and Flash EEPROM cells”. IEDM Tech. Dig., pp. 99-102.

    Google Scholar 

  23. San K.T., Kaya C., Liu D.K.Y., Ma T.P. and Shah P. (1992) “A new technique for determining the capacitive coupling coefficients in FLASH EPROMs”. IEEE Electron Device Letters, 13,6, pp. 328–331.

    Article  Google Scholar 

  24. Moison B., Papadas C., Ghibaudo G., Mortini P. and Pananakakis G. (1993) “New method for the extraction of the coupling ratios in FLOTOX EPROM cells”. IEEE Trans. on Electron Devices, 40,10, pp. 1870–1872.

    Article  Google Scholar 

  25. Woods M. (1991) “An E-PROM’s integrity starts with its cell structure”. C. Hu (Ed.), Nonvolatile semiconductor memories: technologies, design, and application, IEEE Press, Chapter 3, pp. 59-62.

    Google Scholar 

  26. Bez R., Cantarelli D. and Serra S. (1992) “The channel hot electron programming of a floating gate MOSFET: an analytical study”. 12 th Nonvolatile Semiconductor Memory Workshop, Monterey, California (USA).

    Google Scholar 

  27. Bez R., Cantarelli D., Moioli L., Ortolani G., Villa C. and Dallabora M. (1998) “A new erasing method for a single-voltage long-endurance Flash memory”. IEEE Electron Device Letters, 19,2, pp. 37–39.

    Article  Google Scholar 

  28. Cagnina S., Chang C., Haddad S., Lien J., Radjy N., Sun Y., Tang Y., Van Buskirk M. and Wang A. (1992) “A 0.85μm double metal CMOS technology for 5V Flash memories with sector erase”. 12 th Nonvolatile Semiconductor Memory Workshop, Monterey, California (USA).

    Google Scholar 

  29. Yoshikawa K., Yamada S., Miyamoto J., Suzuki T., Oshikiri M., Obi E., Hiura Y., Yamada K., Ohshima Y. and Atsumi S. (1992) “Comparison of current Flash EEPROM erasing methods: stability and how to control”. IEDM Tech. Dig., pp. 595-598.

    Google Scholar 

  30. Keenney S., Bez R., Cantarelli D., Piccinini F., Mathewson A. and Lombardi C. (1992) “Complete transient simulation of Flash EEPROM devices”. IEEE Trans, on Electron Devices, 39,12, pp. 2750–2757.

    Article  Google Scholar 

  31. Cappelletti P., Panchieri A. and Ravazzi L. (1993) “Mastering key factor which affect flash memory reliability”. ESREF 93, Bordeaux (France), pp. 77–82.

    Google Scholar 

  32. Tsai H., Yu C.L. and Wu C.Y. (1986) “A bird’s beak technique for LOCOS in VLSI fabrication”. IEEE Electron Device Letters, 7,2, pp. 122–123.

    Article  Google Scholar 

  33. Wils N.A.H., van der Plas P.A. and Montree A.H. (1990) “Dimensional characterization of poly buffer LOCOS in comparison with suppressed LOCOS”. ESSDERC 90, pp. 535–538.

    Google Scholar 

  34. Guldi R.L., McKee B., Damminga G.M., Young C.Y. and Beals M.A. (1989) “Characterization of poly buffer locos in manufacturing environment”. Journal of Electrochemical Society, 136, p. 3815.

    Article  Google Scholar 

  35. Miéville J.P., Rooyackers R. and Deferm L. (1994) “An optimized poly-buffered LOCOS process for a 0.35μm CMOS technology”. C. Hill and P. Asburn (Eds.), Proc. 24 th ESSDERC 94, pp. 99-202.

    Google Scholar 

  36. Burton G., Tuntasood P., Chien F., Kovacs R. and Vora M. (1984) “New techniques for elimination of the bird’s beak”. IEDM Tech. Dig., pp. 582-585.

    Google Scholar 

  37. Shimizu N., Naito Y., Itoh Y., Shibata Y., Hashimoto K., Nishio M., Asai A., Ohe K., Umimoto H. and Hirofiji Y. (1992) “A poly-buffer recessed LOCOS process for 256Mbit DRAM cells”. IEDM Tech. Dig., pp. 279-282.

    Google Scholar 

  38. Pfiester J.R., Kenkare P.U., Subrahmanyan R., Lin J.H. and Crabtree P. (1993) “Nitride-clad LOCOS isolation for 0.25μm CMOS”. VLSI Tech. Symp., no. 11-2, pp. 139–140.

    Article  Google Scholar 

  39. Borland J.O. and Koelsch R. (1993) “MeV implantation technology: next generation manufacturing with current generation equipment”. Solid State Technology, p. 1.

    Google Scholar 

  40. Cappelletti P., Fratin L. and Ravazzi L. (1995) “Application of advanced ion implantation techniques to Flash memories”. Nuclear Instruments and Methods in Physics Research, B, 96, pp. 405–410.

    Article  Google Scholar 

  41. Auricchio C., Bez R., Losavio A., Maurelli A., Sala C. and Zabberoni P. (1996) “A triple-well architecture for low voltage operation in submicron CMOS devices”. G. Baccarani and M. Rudan (Eds.), Proc. ESSDERC 96, Bologna (Italy), p. 613.

    Google Scholar 

  42. Umezawa A., Atsumi S., Kuryiama M., Banba H., Imamiya K., Naruke K., Yamada S., Obi E., Oshikiri M., Suzuki T. and Tanaka S. (1992) “A 5 V-only operation 0.6μm Flash EEPROM with row decoder scheme in triple-well structure”. IEEE Journal of Solid State Circuits, 27,11, p. 1540.

    Article  Google Scholar 

  43. Momodomi M., Tanaka T., Iwata Y., Tanaka Y., Oodaira H., Itoh Y., Shirota R., Huchi K.O. and Masuoka F. (1991) “A 4Mb NAND EEPROM with tight programmed V t distribution”. IEEE Journal of Solid State Circuits, 26,4, p. 492.

    Article  Google Scholar 

  44. Kobayashi K., Nakai H., Kunori Y., Nakayama T., Miyawakiand Y., Terada Y., Onoda H., Ajika N., Hatanaka M., Miyoshi H. and Yoshihara T. (1993) “Memory array architecture and decoding scheme for 3 V-only sector erasable DINOR flash memory”. VLSI Circuit Digest Technical Papers, p. 93.

    Google Scholar 

  45. Uchiyama A., Fukuda H., Hayashi T., Iwabuchi T. and Ohno S. (1990) “High performance dual-gate sub-half micron CMOS with 6 nm thick ni-trided SiO2 films in N2O ambient”. IEDM Tech. Dig., pp. 425-428.

    Google Scholar 

  46. Fukuda H., Arakawa T. and Ohno S. (1990) “High reliable thin nitride films formed by rapid thermal processing in N2O ambient”. Journal of Applied Physics, 29,12, p. L2333.

    Google Scholar 

  47. Ting W., Hwang H., Lee J. and Kwong D. (1990) “Composition and growth kinetics of ultrathin SiO2 by oxidizing Si substrate in N2O”. Applied Physics Letters, 57, p. 26.

    Google Scholar 

  48. Bellafiore N., Pio F. and Riva C. (1993) “Thin oxide nitridation in N2O by RTP for non-volatile memories”. Microelectronics Journal, 24, p. 453.

    Article  Google Scholar 

  49. Dunn G. and Scott S.A. (1990) “Channel hot-carrier stressing of reoxidized nitrided silicon dioxide”. IEEE Trans, on Electron Devices, 37,7, p. 1719.

    Article  Google Scholar 

  50. Pan C., Wu K.J., Freiberger P.P., Chatterjee A. and Sery G. (1990) “A scaling methodology for oxide-nitride-oxide interpoly dielectric for EPROM applications”. IEEE Trans,.on Electron Devices, 37,6, p. 1439.

    Article  Google Scholar 

  51. Pan C., Yu K.W. and Sery G. (1991) “Physical origin of long-term charge loss in floating-gate EPROM with interpoly oxide-nitride-oxide stacked dielectric”. IEEE Electron Device Letters, 12,2, p. 51.

    Article  Google Scholar 

  52. Mori S., Sakagami E., Araki H., Kaneko Y., Narita K., Ohshima Y., Arai N. and Yoshikawa K. (1991) “ONO interpoly dielectric scaling for nonvolatile memory applications”. IEEE Trans, on Electron Devices, 38,2, pp. 386–391.

    Article  Google Scholar 

  53. Tang Y., Chen J., Chang C., Liu D., Haddad S., Sun Y., Wang A., Ramskey M., Kwong M., Kinoshita H., Chan W. and Lien J. (1996) “Different dependence of band-to-band and Fowler-Nordheim tunneling on source doping concentration of an n-MOSFET”. IEEE Electron Device Letters, 17,11, p. 525.

    Article  Google Scholar 

  54. Cappelletti P., Cutolo A., Fratin L., Ravazzi L. and Riva C. (1995) “The Flash E2PROM cell with Boron p-pocket architecture: advantages and limitations”. Proc. Nonvolatile Semiconductor Memory Workshop.

    Google Scholar 

  55. Crisenza G., Ghidini G., Manzini S., Modelli A. and Tosi M. (1990) “Charge loss in EPROM due to ion generation and transport in interlevel dielectrics”. IEDM Tech. Dig., p. 107.

    Google Scholar 

  56. Crisenza G., Clementi C., Ghidini G. and Tosi M. (1992) “Floating gate memories reliability”. Quality and reliability engineering international, 8, 177.

    Article  Google Scholar 

  57. Ohmi T., Miyashita M. and Imaoka T. (1991) Proc. Microcontamination 91, pp. 491–510, 1991.

    Google Scholar 

  58. Tissier A. et al. (1994) “Planarization of pre-metal and metal levels for 0.5μm and 0.35μm logic CMOS processes”. Proc. Conferences on Advanced Metallization for ULSI Application MRS.

    Google Scholar 

  59. Bai G., Chiang C., Cox N., Fang S., Gardner D.S., Mack A. and Marieb T. (1996) “Copper interconnection deposition techniques and integration”. Proc. 1996 Symposium on VLSI Technology, Honolulu, pp. 48-49.

    Google Scholar 

  60. Morand Y., Lerme M., Palleau J., Torres J., Vinet F., Demolliens O., Ulmer L., Gobil G., Fayolle M., Romagna F. and Bihan R.L. (1997) “Copper integration in self aligned dual damascene architecture”. Proc. 1997 Symposium on VLSI Technology, Kyoto (Japan), pp. 31-32.

    Google Scholar 

  61. Cappelletti P., Bez R., Cantarelli D. and Fratin L. (1994) “Failure mechanisms of Flash cell in program/erase cycling”. IEDM Tech. Dig., pp. 291-294.

    Google Scholar 

  62. Haddad S., Chang C., Swaminathan B. and Lien J. (1989) “Degradation due to hole trapping in Flash memory cells”. IEEE Electron Device Letters, 10,3, pp. 117–119.

    Article  Google Scholar 

  63. Yamada S., Hiura Y., Yamane T., Amemiya K., Oshima Y. and Yoshikawa K. (1993) “Degradation mechanism of Flash EEPROM programming after program/erase cycles”. IEDM Tech. Dig., pp. 23-26.

    Google Scholar 

  64. Olivo P., Riccò B. and Sangiorgi E. (1986) “High field induced voltage dependent oxide charge”. Applied Physics Letters, 48, pp. 1135–1137.

    Article  Google Scholar 

  65. Esseni D., Selmi L., Bez R., Ravazzi L. and Sangiorgi E. (1995) “Soft-programming in scaled flash memory cells”. H.C. de Graaf and H.V. Kranemburg (Eds.), Proc. ESSDERC 95, The Hague (The Netherlands), pp. 549-552.

    Google Scholar 

  66. Van Houdt J.F., Wellekens D., Groeseneken G. and Maes H.E. (1995) “Investigation of the soft-write mechanism in source side injection flash EEPROM devices”. IEEE Electron Device Letters, 16, p. 181.

    Article  Google Scholar 

  67. Aritome S., Shirota R., Hemnik G., Endoh T. and Masuoka F. (1993) “Reliability issues of Flash memory cells”. Proc. of the IEEE, 81,5, pp. 776–788.

    Article  Google Scholar 

  68. Ong T.C., Fazio A., Mielke N., Pan S., Righos N., Atwood G. and Lai S. (1993) “Erratic erase in ETOX Flash memory array”. VLSI Symp. on Tech., pp. 82-83.

    Google Scholar 

  69. Dunn C., Kaya C., Lewis T., Strauss T., Schreck J., Hefley P., Middendorf M. and San T. (1994) “Flash EPROM disturb mechanism”. Proc. IRPS, pp. 299-308.

    Google Scholar 

  70. Crisenza G., Annunziata R., Camerlenghi E. and Cappelletti P. (1996) “Non volatile memories: issues, challenges and trends for the 2000’s scenario”. Proc. ESSDERC ′96, Bologna (Italy), pp. 121–130.

    Google Scholar 

  71. Moazzami R. and Hu C. (1992) “Stress-induced current in thin silicon dioxide films”. IEDM Tech. Dig., pp. 139-142.

    Google Scholar 

  72. Maramatsu S., Kubota T., Nishio N., Shirai H., Matsuo M., Kodama N., Horikawa M., Saito S., Arai K. and Okazawa T. (1994) “The solution of over-erase problem controlling poly-Si grain size modified principles for Flash memories”. IEDM Tech. Dig., pp. 847-850.

    Google Scholar 

  73. Mitchell A.T., Huffman C. and Esquivel A.L. (1987) “A new self-aligned planar array cell for ultra high density EPROMs”. IEDM Tech. Dig., pp. 548-553.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

Copyright information

© 1999 Springer Science+Business Media New York

About this chapter

Cite this chapter

Pavan, P., Bez, R. (1999). The Industry Standard Flash Memory Cell. In: Flash Memories. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-5015-0_2

Download citation

  • DOI: https://doi.org/10.1007/978-1-4615-5015-0_2

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-7923-8487-8

  • Online ISBN: 978-1-4615-5015-0

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics