Abstract
The rapid development of integrated circuit fabrication technologies and the growing need for faster and more sophisticated data processing have produced an exponential growth in the complexity of VLSI circuits over the past three decades. Nowadays, it is possible to implement integrated circuits with hundreds of millions of transistors fabricated in technologies permitting minimum feature sizes around and below 100 nanometers (0.10 μm). As increasingly greater circuit complexity and functionality are demanded by exciting new applications, the ability to design complex VLSI and ULSI circuits—thereby fully utilizing the potential of these technologies—is strongly restricted by physical phenomena at the circuit and system level. Increasingly important to the design process is not only human knowledge but also the use of sophisticated Computer-Aided Design (CAD) tools. These tools are crucial to synthesizing and analyzing circuits with predictable performance and quality.
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The interconnections of specific logic gates and registers.
Maximum clock frequency or minimum clock period.
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© 2000 Springer Science+Business Media New York
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Kourtev, I.S., Friedman, E.G. (2000). Conclusions. In: Timing Optimization Through Clock Skew Scheduling. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-4411-1_9
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DOI: https://doi.org/10.1007/978-1-4615-4411-1_9
Publisher Name: Springer, Boston, MA
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Online ISBN: 978-1-4615-4411-1
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