Abstract
Many studies have shown that significant amounts of parallelism can be extracted from ordinary programs if a processor can accurately look ahead arbitrarily far into the dynamic instruction stream. Control flow changes caused by conditional branches are a major impediment to determining which of the distant instructions belong to the dynamic instruction stream. This chapter deals with the use of control independence information for extracting this “distant parallelism”. The two major contributions of the chapter are: (i) demonstration of control independence as a viable means to extract distant parallelism, and (ii)detailed characterization of control independence, in terms of granularity and the available parallelism at each granularity level. The frequency data (on control independence granularity) presented is a first step in determining what situations require special attention. This knowledge can be applied to the development of specialized hardware architectures that can utilize control independences at different granularity levels.
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References
T. M. Austin and G. S. Sohi, “Dynamic Dependency Analysis of Ordinary Programs,” Proc. 19th Annual International Symposium on Computer Architecture, pp. 342–351, 1992.
R. Cytron, J Ferrante, B. Rosen, M. Wegman, and F. Zadeck, “Efficiently Computing Static Single Assignment Form and the Control Dependence Graph,” ACM Transactions on Programming Languages and Systems, Vol. 13, No. 4, pp. 451–490, October 1991.
P. Dubey, K. O’Brien, K. M. O’Brien, and C. Barton, “Single-Program Speculative Multithreading (SPSM) Architecture: Compiler-assisted Fine-Grained Multithreading,” Proc. International Conference on Parallel Architecture and Compilation Techniques (PACT’ 95), 1995.
M. Franklin, “The Multiscalar Architecture,” Ph.D. Thesis, Technical Report 1196, Computer Sciences Department, University of Wisconsin-Madison, 1993.
M. Franklin, “Multi-Version Caches for Multiscalar Processors,” Proc. International Conference on High Performance Computing, p-p. 99–104, 1995.
M. Franklin and G. S. Sohi, “ARB: A Hardware Mechanism for Dynamic Memory Disambiguation,” IEEE Transactions on Computers,Vol. 45, No. 5, pp. 552–571, May 1996.
S. Jayashree and S. Vajapeyam, “Exploiting Parallelism across Basic Blocks via Decoupled Control Flow,” Technical Report TR No.IISc-CSA-95-01, Department of Computer Science and Automation, Indian Institute of Science, March 21, 1995.
M. S. Lam and R. P. Wilson, “Limits of Control Flow on Parallelism,” Proc. 19th Annual International Symposium on Computer Architecture, pp. 46–57, 1992.
M. H. Lipasti and J. P. Shen, “Exceeding the Dataflow Limit via Value Prediction,” Proc. 29th International Symposium on Microar-chitecture (MICRO-29), pp. 226–237, 1996.
S. A. Mahlke, R. E. Hank, R. A. Bringmann, J. C. Gyllenhaal, D. M. Gallagher, and W. W. Hwu, “Characterizing the Impact of Predicated Execution on Branch Prediction,” Proc. 27th International Symposium on Microarchitecture, pp. 217–227, 1994.
R. K. Montoye, E. Hokenek, and S. L. Runyon, “Design of the IBM RISC System/6000 Floating-Point Execution Unit,” IBM Journal of Research and Development, Vol. 34, No. 1, pp. 59–70, January 1990.
J. T. Oplinger, D. L. Heine, and M. S. Lam, “In Search of Speculative Thread-Level Parallelism,” Proc. International Conference on Parallel Architecture and Compilation Techniques (PACT’ 99), 1999.
M. Postiff, D. Greene, G. Tyson, and T. Mudge, “The limits of instructions level parallelism in SPEC95 applications,” Proc. 3rd Workshop on Interaction Between Compilers and Computer Architecture (INTERACT-3), 1998.
E. Rotenberg, Q. Jacobson, and J. E. Smith, “A Study of Control Independence in Superscalar Processors,” Proc. 5th International Symposium on High Performance Computer Architecture (HPCA), 1999.
G. S. Sohi, S. E. Breach, and T. N. Vijaykumar, “Multiscalar Processors,” Proc. 22nd International Symposium on Computer Architecture, pp. 414–425, 1995.
K. B. Theobald, G. R. Gao, and L. J. Hendren, “On the Limits of Program Parallelism and its Smoothability,” Proc. 25th Annual International Symposium on Microarchitecture (MICRO-25), pp. 10–19, 1992.
D. M. Tullsen, S.J. Eggers, and H.M. Levy, “Simultaneous Multithreading: Maximizing On-Chip Parallelism,” proc. 22nd Annual International Symposium on Computer Architecture, pp. 392–403, 1995.
T. N. Vijaykumar and G. S. Sohi, “Task Selection in a Multiscalar Processor,” Proc. 31st International Symposium on Microarchitecture, 1998.
T-Y. Yeh and Y. N. Patt, “Alternative Implementations of Two-Level Adaptive Branch Prediction,” Proc. 19th Annual International Symposium on Computer Architecture, pp. 124–134, 1992.
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Bhowmik, A., Franklin, M. (2000). A Characterization of Control Independence in Programs. In: John, L.K., Maynard, A.M.G. (eds) Workload Characterization for Computer System Design. The Springer International Series in Engineering and Computer Science, vol 542. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-4387-9_8
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DOI: https://doi.org/10.1007/978-1-4615-4387-9_8
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