The Catree Architectural Synthesis with Testability

  • Catherine H. Gebotys
  • Mohamed I. Elmasry
Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 158)


Two VLSI testable architectural synthesis methodologies with testability, area, and delay constraints are presented in this chapter. This research differs from other synthesizers by
  1. 1)

    implementing testability as of the synthsizad VLSI arvchitectural solution,

  2. 2)

    providing feedback to the synthesis process, and

  3. 3)

    by integrating test incorporation with architectural synthesis(specifi-cally allocation and binding) using tree data structure.



Functional Unit Design Solution Test Vector Test Methodology Fault Coverage 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media New York 1991

Authors and Affiliations

  • Catherine H. Gebotys
    • 1
  • Mohamed I. Elmasry
    • 1
  1. 1.University of WaterlooWaterlooCanada

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