Synthesis of Self-Timed Circuits

  • Teresa H. Meng
Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 123)


This chapter describes a synthesis procedure of designing digital systems that do not require the distribution of a clocking signal. Guarded commands [1] were chosen to provide a simple syntax for circuit specifications. The notation of signal transition graphs [2] was used to represent circuit behavior and to simplify algorithms and graph manipulations. The definition of semi-modularity [3] was modified and the theorems developed for marked directed graphs [4] were used to guarantee a hazard-free implementation. All together, a deterministic algorithm of synthesizing self-timed synchronization circuits from high-level specifications was constructed. The implication is that fully asynchronous design (or more precisely, asynchronous design using anisochronous interconnect according to the previous chapter) is feasible and self-timed circuit synthesis can be automated. Although in this chapter we are primarily concerned with the synthesis of non-metastable circuits, the procedure is also valid for metastable circuit synthesis.


Boolean Function State Diagram Boolean Expression Reachability Graph Computation Block 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    E. W. Dijkstra, “Guarded Commands, Nondeterminacy and Formal Derivation of Programs,” Communications of the ACM 18(8) pp. 453–457 (Aug. 1975).MathSciNetMATHCrossRefGoogle Scholar
  2. 2.
    T. A. Chu, “Synthesis of Self-Timed Control Circuits from Graphs: An Example,” Proc. IEEE 1986 ICCD, pp. 565–571 (Oct. 1986).Google Scholar
  3. 3.
    R. E. Miller, Switching Theory, John Wiley & Sons, Inc., New York (1965).Google Scholar
  4. 4.
    F. Commoner and A. W. Holt, “Marked Directed Graphs,” Journal of Computer and System Sciences 5 pp. 511–523 (1971).MathSciNetMATHCrossRefGoogle Scholar
  5. 5.
    J. van de Snepscheut, “Trace Theory and VLSI Design,” Lecture Notes on Computer Science 200, Springer-Verlag, (1985).MATHGoogle Scholar
  6. 6.
    J. C. Ebergen, “A formal Approach to Designing Delay-Insensitive Circuits,” Computer Science Notes, Eindhoven University of Technology, (October 1988).Google Scholar
  7. 7.
    A. J. Martin, “Compiling Communicating Processes into Delay-Insensitive VLSI Circuits,” Distributed Computing 1 pp. 226–234 (1986).MATHCrossRefGoogle Scholar
  8. 8.
    D. Misunas, “Petri Nets and Speed Independent Design,” Communications of ACM 16(8) pp. 474–481 (Aug. 1973).CrossRefGoogle Scholar
  9. 9.
    T. S. Balraj and M. J. Foster, “Miss Manners: A Specialized Silicon Compiler for Synchronizers,” Advanced Research in VLSI, The MIT Press, (April 1986).Google Scholar
  10. 10.
    T. H.-Y. Meng, R. W. Brodersen, and D. G. Messerschmitt, “Automatic Synthesis of Asynchronous Circuits from High Level Specifications,” Submitted to IEEE Trans. on CAD, (July 1987).Google Scholar
  11. 11.
    C. L. Seitz, “Self-Timed VLSI Systems,” Proc. of the Cal Tech Conference on VLSI, (Jan. 1979).Google Scholar
  12. 12.
    D. E. Muller, “Infinite Sequences and Finite Machines,” Proc. 4th Annual IEEE Symposium on Switching Circuit Theory and Logical Design S-156 pp. 9–16 (Sept. 1963).Google Scholar
  13. 13.
    S. H. Unger, Asynchronous Sequential Switching Circuits, WileyInterscience, John Wiley & Sons, Inc., New York (1969).Google Scholar
  14. 14.
    A. J. Martin, “The Limitations to Delay-Insensitivity in Asynchronous Circuits,” Proc. of the Sixth MIT Conference in Advanced Research in VLSI, pp. 263–278 (May 1990).Google Scholar
  15. 15.
    L. G. Heller and W. R. Griffin, “Cascode Voltage Switch Logic: A Differential CMOS Logic Family,” 1984 IEEE ISSCC Digest of Technical Papers, (Feb. 1984).Google Scholar
  16. 16.
    G. Jacobs and R. W. Brodersen, “Self-Timed Integrated Circuits for Digital Signal Processing Applications,” VLSI Signal Processing III, IEEE PRESS, (November, 1988).Google Scholar
  17. 17.
    R. K. Brayton and C. McMullen, “Decomposition and Factorization of Boolean Expressions,” Proc. IEEE ICAS, (May, 1982).Google Scholar
  18. 18.
    C. K. Erdelyi, W. R. Griffin, and R. D. Kilmoyer, “Cascode Voltage Switch Logic Design,” VLSI Design, (October 1984).Google Scholar
  19. 19.
    T. H.-Y. Meng, R. W. Brodersen, and D. G. Messerschmitt, “Implementation of High Sampling Rate Adaptive Filters Using Asynchronous Design Techniquess,” VLSI Signal Processing III, IEEE PRESS, (November, 1988).Google Scholar
  20. 20.
    D. E. Muller and W. S. Barsky, “A Theory of Asynchronous Circuits,” Proc. of International Symposium of the Theory of Switching, pp. 204–243 Harvard University Press, (1959).Google Scholar
  21. 21.
    D. B. Gillies, “Flow Chart Notation for the Description of a Speed Independent Control,” Proc. 2nd Annual IEEE Symposium on Switching Circuit Theory and Logical Design S-134(Oct. 1961).Google Scholar
  22. 22.
    R. E. Swartwout, “One Method for Designing Speed Independent Logic for a Control,” Proc. 2nd Annual IEEE Symposium on Switching Circuit Theory and Logical Design S-134 (Oct. 1961).Google Scholar
  23. 23.
    R. E. Swartwout, “New Techniques for Designing Speed Independent Control Logic,” Proc. 5th Annual IEEE Symposium on Switching Circuit Theory and Logical Design S-164(Nov. 1964).Google Scholar
  24. 24.
    T. Agerwala, “Putting Petri Nets to Work,” IEEE Computer, pp. 85–94 (Dec. 1979).Google Scholar
  25. 25.
    J. B. Dennis, “Modular, Asynchronous Control Structure for a High Performance Processor,” Record of Project MAC Conf. Concurrent and Parallel Computation, ACM, pp. 55–80 (1970).Google Scholar
  26. 26.
    S. S. Patil and J. B. Dennis, “The Description and Realization of Digital Systems,” IEEE COMPCON 72, Digest of Papers, pp. 223–226 (1972).Google Scholar
  27. 27.
    J. L. Peterson, “Petri Nets,” Computing Surveys 9(3) pp. 221–252 (Sept. 1977).Google Scholar
  28. 28.
    R. M. Keller, “Towards a Theory of Universal Speed-Independent Modules,” IEEE Trans. on Computers C-23(1) pp. 21–33 (Jan. 1974).MATHCrossRefGoogle Scholar
  29. 29.
    A. S. Wojcik and K.-Y Fang, “On the Design of Three-Valued Asynchronous Modules,” IEEE Trans. on Computers C-29(10)(Oct. 1980).Google Scholar
  30. 30.
    T. M. Carter, “AS SANSSIN: An Assembly, Specification and Analysis System for Speed Independent Control-Unit Design in Integrated Circuits Using PPL,” Master’ s Thesis, Department of Computer Science, University of Utah, (June 1982). 65Google Scholar
  31. 31.
    D. L. Dill and E. M. Clarke, “Automatic Verification of Asynchronous Circuits Using Temporal Logic,” Proc. 1985 Chapel Hill Conference on Very Large Scale Integration, pp. 127–143 Computer Science Press, (1985).Google Scholar
  32. 32.
    D. M. Chapiro, “Globally-Asynchronous Locally-Synchronous Systems,” Ph.D. Thesis, (STAN-CS-1026)Stanford University, (Oct. 1986).Google Scholar
  33. 33.
    A. J. Martin, “The Design of a Self-Timed Circuit for Distributed Mutual Exclusion,” Proc. 1985 Chapel Hill Conference on Very Large Scale Integration, pp. 245–283 Computer Science Press, (1985).Google Scholar
  34. 34.
    M. Hack, “Analysis of Production Schemata by Petri Nets,” MAC TR-94, Project MAC, MIT, (Feb. 1972).Google Scholar
  35. 35.
    E. B. Eichelberger, “Hazard Detection in Combinational and Sequential Switching Circuits,” IBM Journal, (March 1965).Google Scholar
  36. 36.
    C. Mead and L Conway, Chap. 7, Introduction to VLSI Systems, Addison-Wesley Publishing Company (1980).Google Scholar
  37. 37.
    S. Y. Kung and R. J. Gal-Ezer, “Synchronous versus Asynchronous Computation in Very Large Scale Integration Array Processors,” SPIE, Real Time Signal Processing V 341(1982).Google Scholar
  38. 38.
    C. A. R. Hoare, “Communicating Sequential Processes,” Communications of the ACM 21(8) pp. 666–677 (Aug. 1978).MathSciNetMATHCrossRefGoogle Scholar
  39. 39.
    B. C. Kuszmaul, “A Glitch in the Theory of Delay-Insensitive Circuits,” Proc. of ACM Workshop on Timing Issues in the Specifiation and Synthesis of Digital Systems (TAU ‘80), (August 1990Google Scholar
  40. 40.
    R. L. Rudell and A. Sangiovanni-Vincentelli, “Multiple-Valued Minimization for PLA Optimization,” IEEE Trans. on CAD/ICAS, (September 1987).Google Scholar
  41. 41.
    S. Bums, Private Communications, (May 1988).Google Scholar
  42. 42.
    A. J. Martin, Private Communications, (May 1988).Google Scholar
  43. 43.
    C. Berthet and E. Cerny, “An Algebraic Model for Asynchrnous Circuits Verifications,” Trans. on Computers COM-37(7) pp. 835–847 (July 1988).CrossRefGoogle Scholar
  44. 44.
    T. A. Chu, “A Method of Abstraction for Petri Nets,” International Workshop in Petri Nets and Performance Models, (Aug. 1987).Google Scholar

Copyright information

© Springer Science+Business Media New York 1991

Authors and Affiliations

  • Teresa H. Meng
    • 1
  1. 1.Stanford UniversityUSA

Personalised recommendations