Abstract
Those who design high-performance architectures today must design machines in such a way that compiler technology can exploit the power of their architectures—often through parallelism at many different levels. Moreover, new compiler concepts and techniques are needed to cope with rapidly advancing hardware technology. In fact, recent architectural breakthroughs have been directly related to innovative compiler optimizations—whether it be for reduced instruction set computers (RISC), complex instruction set computers (CISC), multiprocessing, or vector processing.
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© 1991 Springer Science+Business Media New York
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Gao, G.R. (1991). Efficient Dataflow Software Pipelining. In: A Code Mapping Scheme for Dataflow Software Pipelining. The Kluwer International Series in Engineering and Computer Science, vol 125. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3988-9_12
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DOI: https://doi.org/10.1007/978-1-4615-3988-9_12
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6782-6
Online ISBN: 978-1-4615-3988-9
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