Univ. of California at Irvine’s VSS

  • Robert A. Walker
  • Raul Camposano
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 135)


The University of California at Irvine’s VHDL Synthesis System (VSS) produces Register Transfer level designs, which can then passed on to the Microarchitecture and Logic Optimizer (MILO) system for optimization and library binding. The VSS includes transformations, scheduling, data path synthesis, and functional synthesis.


Control Step Full Adder Controlflow Graph Register Transfer Behavioral Description 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. Rundensteiner90.
    Elke A. Rundensteiner, Daniel D. Gajski, and Lubomir Bic, “The Component Synthesis Algorithm: Technology Mapping for Register Transfer Descriptions”, Proc. of ICCAD’90, pages 208–211, November 1990.Google Scholar
  2. Potasman90.
    Roni Potasman, Joseph Lis, Alexandru Nicolau, and Daniel Gajski, “Percolation Based Synthesis”, Proc. of the 27th DAC, pages 444–449, June 1990.Google Scholar
  3. Lis89.
    Joseph S. Lis and Daniel D. Gajski, “VHDL Synthesis Using Structured Modeling”, Proc. of the 26th DAC, pages 606–609, June 1989.Google Scholar
  4. Lis88.
    Joseph S. Lis and Daniel D. Gajski, “Synthesis from VHDL”, Proc. of ICCD’88, pages 378–381, October 1988.Google Scholar
  5. Orailoglu86.
    Alex Orailoglu and Daniel D. Gajski, “Flow Graph Representation”, Proc. of the 23rd DAC, pages 503–509, June 1986.Google Scholar

Copyright information

© Springer Science+Business Media New York 1991

Authors and Affiliations

  • Robert A. Walker
    • 1
  • Raul Camposano
    • 2
  1. 1.Rensselaer Polytechnic InstituteUSA
  2. 2.IBMUSA

Personalised recommendations