Skip to main content

Abstract

Since they were first introduced in the IBM 360/85 in 1969, the primary application of cache memories has been in the general purpose computing community. Thus, it is no surprise that modern cache designs are optimized for average case performance. This optimization criterion has opened a wide gap between the average case performance which is important to general purpose computing and the worst case performance that is critical to real-time computing. This has delayed the adoption of caches by the real-time community. The SMART (Strategic Memory Allocation for Real-Time) cache design approach narrows the gap between this worst case performance, and the impressive average case performance provided by conventional caches. This paper focuses on an analytical approach to cache allocation which minimizes task set utilization while guaranteeing schedulability. An overview of the SMART caching strategy is presented, as well as an algorithm which optimally allocates cache segments to a set of periodic tasks using rate monotonic scheduling. This algorithm uses dynamic programming to reduce an exponential search space to a polynomial one. Results which show SMART caches narrowing the gap between average and worst case performance to less than 10% are then presented.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. A. Agarwal, R. Simoni, J. Hennessy, and M. Horowitz. An Evalua-tion of Directory Schemes for Cache Coherence. In The 15th Annual International Symposium on Computer Architecture Conference Proceedings, pages 280–289. IEEE, Hoholulu, Hawaii, May, 1988.

    Chapter  Google Scholar 

  2. Gilles Brassard and Paul Bratley. Algorithmics: theory and practice. Prentice-Hall, Englewood Cliffs, NJ, 1988.

    Google Scholar 

  3. D. W. Clark, B. W. Lampson, and K. A. Pier. The memory system of a high performance personal computer. IEEE Transactions on Computers TC-30(10):715–733, October, 1981.

    Article  Google Scholar 

  4. James R. Goodman. Using Cache Memory to Reduce Processor- Memory Traffic. In The 10th Annual International Symposium on Computer Architecture Conference Proceedings, pages 124–131. IEEE, Hoholulu, Hawaii, June, 1983.

    Google Scholar 

  5. Mark D. Hill. Dinero HI Cache Simulator: Version 3.1 Computer Science Dept, Univ. of Wisconsin, Madison, WI, 1985.

    Google Scholar 

  6. Mark Hill. A Case for Direct Mapped Caches. IEEE Computer 21(12):25–40, December, 1988.

    Article  Google Scholar 

  7. David B. Kirk. SMART (Strategic Memory Allocation for Real- Time) Cache Design. PhD Thesis Proposal. December, 1988 Carnegie-Mellon University.

    Google Scholar 

  8. David B. Kirk. Process Dependent Static Cache Partitioning for Real-Time Systems. In Proceedings of the Real-Time Systems Symposium, pages 181–190. IEEE, Huntsville, AL, December, 1988.

    Google Scholar 

  9. David B. Kirk. SMART (Strategic Memory Allocation for Real-Time) Cache Design. In Proceedings of the Real-Time Systems Symposium,pages 229–237. IEEE, Santa Monica, CA, December, 1989.

    Google Scholar 

  10. David B. Kirk. Predictable Cache Design for Real-Time Systems. PhD thesis, Carnegie Mellon University, December, 1990.

    Google Scholar 

  11. David B. Kirk, Jay K. Strosnider. SMART (Strategic Memory Allocation for Real-Time) Cache Design Using the R3000. In Proceedings of the Real-Time Systems Symposium. Orlando, FA, December, 1990.

    Google Scholar 

  12. J. P. Lehoczky, L. Sha, and Y. Ding. The Rate Monotonic Scheduling Algorithm --- Exact Characterization and Average Case Behavior. In Proceedings of the Real-Time Systems Symposium, pages 166–171. IEEE, Santa Monica, CA, December, 1989.

    Chapter  Google Scholar 

  13. C. L. Liu and James W. Layland. Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment. Journal of the Association for Computing Machinery 20(1):46–61, January, 1973.

    Article  MathSciNet  MATH  Google Scholar 

  14. Alan J. Smith. Cache Memories. ACM Computing Surveys 14(3):473–530, September, 1982.

    Article  Google Scholar 

  15. Alan J. Smith. Cache memory design: an evolving art. IEEE Spectrum 24(12):40–44, December, 1987.

    Google Scholar 

  16. Kimming So, Rudolph N. Rechtschaffen. Cache Operations by MRU Change. IEEE Transactions on Computers 37(6):700–709, June, 1988.

    Article  Google Scholar 

  17. Paul Sweazy and Alan Smith. A Class of Compatible Cache Consistency Protocols and their Support by the IEEE Futurebus. In The 13th International Symposium on Computer Architecture Conference Proceedings pages 414–423. IEEE, Tokyo, Japan, June, 1986.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 1991 Springer Science+Business Media New York

About this chapter

Cite this chapter

Kirk, D.B., Strosnider, J.K., Sasinowski, J.E. (1991). Allocating Smart Cache Segments for Schedulability. In: van Tilborg, A.M., Koob, G.M. (eds) Foundations of Real-Time Computing: Scheduling and Resource Management. The Springer International Series in Engineering and Computer Science, vol 141. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3956-8_9

Download citation

  • DOI: https://doi.org/10.1007/978-1-4615-3956-8_9

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-6766-6

  • Online ISBN: 978-1-4615-3956-8

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics