A Highly Parallel Digital Architecture for Neural Network Emulation

Abstract

This paper discusses a new VLSI architecture for emulating neural networks. It consists of a SIMD array of simple DSP like processor nodes. By using low-precision arithmetic, an optimized PN architecture,and simple broadcast communication, a large number of processors can be placed onto a single piece of silicon, thus allowing cost-effective,high-performance network emulation. The resulting architecture allows the emulation of arbitrary neural network function, including powerful on-chip learning, and non-neural network data pre-processing and post-processing.