Abstract
In this paper,we describe a proposed hardware implementation for a novel neural network chip. Our design uses probabilistic bit streams to represent the real valued quantities processed by the network. We show that the use of this representation means that each neuron requires only very simple digital circuitry to perform the weighted combination of the inputs and calculate a suitable activation function. The fully digital nature of the design allows the use of well established CMOS VLSI techniques. The mathematical theory supporting the operation of this device is dealt with in a companion paper.
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References
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Max van Daalen and John Shawe-Taylor, “Generating real time probabilistic bit streams”, in preparation.
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© 1991 Springer Science+Business Media New York
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van Daalen, M., Jeavons, P., Shawe-Taylor, J. (1991). Probabilistic Bit Stream Neural Chip: Implementation. In: Delgado-Frias, J.G., Moore, W.R. (eds) VLSI for Artificial Intelligence and Neural Networks. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3752-6_28
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DOI: https://doi.org/10.1007/978-1-4615-3752-6_28
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6671-3
Online ISBN: 978-1-4615-3752-6
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