Abstract
This paper is devoted to a digital special-purpose hardware implementation of an associative memory based on distributed storage of information. The cascadable semi-parallel architecture can be easily extended to large scale memories with several millions of storage elements. The memory has a matrix structure with binary elements (connections) and performs a pattern mapping or completion of binary input/output patterns. Though the memory concept is very simple, it has an attractive asymptotic storage efficiency of 0.69•m•n Bits and the number of patterns that can be stored with low error probability is much larger than the number of columns (artificial neurons).
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Rückert, U., Kleerbaum, C., Goser, K. (1991). Digital VLSI Implementations of an Associative Memory Based on Neural Networks. In: Delgado-Frias, J.G., Moore, W.R. (eds) VLSI for Artificial Intelligence and Neural Networks. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3752-6_27
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DOI: https://doi.org/10.1007/978-1-4615-3752-6_27
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