Abstract
A description is given of a parallel computer architecture called E and its implementation as a full custom design in 2µm VLSI technology. The architecture is highly parallel, consisting of many simple processing elements heavily interconnected. The processing elements perform threshold computations on thousands of inputs. This architecture was inspired by research under the “neural network” banner and retains the highly interconnected nature of such systems. However, it differs from them in some key areas. The ∑ architecture is digital, it provides greater functionality with respect to the type of threshold comparison done, the connection weights remain static for the duration of a problem, and its processing is deterministic. Communication between units is in single bit values which are heavily multiplexed to reduce the amount of physical interconnect and pinout.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Cleary, J.G. “Connectionist Architectures”, Research Report 86/234/8, Department of Computer Science, University of Calgary, 1986.
Cleary, J.G. “A Simple VLSI Connectionist Architecture”, IEEE First International Conference on Neural Networks, San Diego, pp 419–426, 1987.
Fairbairn, D.G.. “VLSI: A New Frontier for Systems Designers”, IEEE Computer, vol. 15(1), pp. 9–24, January 1982.
Glasser, L.A. and Dobberpuhl, D.W., The Design and Analysis of VLSI Circuits,Addison-Wesley, Reading, MA, 1985.
Holt, C.M., Stewart, V., Clint, M. and Perrot, R.H., “An Improved Parallel Thinning Algorithm”, Communications of the ACM, vol. 18(2), pp. 255–264, 1987.
Sahebkar, M., “An Analysis of Algorithms for a Connectionist Architecture”, Project Report Department of Computer Science, University of Calgary, 1987.
Williams, S.R. “The VLSI Implementation of a Fine-Grained Parallel Architecture”, MSc Thesis, also available as Research Report 90/391/15, Department of Computer Science, University of Calgary, 1990.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1991 Springer Science+Business Media New York
About this chapter
Cite this chapter
Williams, S.R., Cleary, J.G. (1991). The VLSI Implementation of the ∑ Architecture. In: Delgado-Frias, J.G., Moore, W.R. (eds) VLSI for Artificial Intelligence and Neural Networks. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3752-6_25
Download citation
DOI: https://doi.org/10.1007/978-1-4615-3752-6_25
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6671-3
Online ISBN: 978-1-4615-3752-6
eBook Packages: Springer Book Archive