Register-Transfer Level Synthesis

Abstract

The result of high-level synthesis is typically an initial description at the RT-level of a data path and a controller. RT-level descriptions mostly characterize a system definition in terms of registers, multiplexors, and operations, as is explained in Chapter 1. These descriptions have already incorporated a notion of a specific architecture and a clocking scheme. Hence, an initial assignment of operations to clocking cycles has been made. The coarse timing frame has been fixed by the scheduling (cf. Chapter 6), but at this level of abstraction further optimization steps may change these initial choices slightly. At this design stage, the physical design characteristics of the various blocks are known in more detail than at the algorithmic level, thus permitting optimization steps which are based on more realistic design models than those that are available for high-level synthesis. RT-level descriptions, on the other hand, form the input to logic-level synthesis, for which the system is specified by blocks of combinational logic and storage elements. In the following, techniques for data path synthesis and controller synthesis are presented.