Abstract
In this chapter, we extend our layout theory to arrays of two or more cells. We first define a practical cell-array layout style and present an algorithm HRMTrailTrace that generates cell arrays optimal in width and height in our layout style. We prove this optimality claim and present experimental results to substantiate it [MH91].
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 1992 Springer Science+Business Media New York
About this chapter
Cite this chapter
Maziasz, R.L., Hayes, J.P. (1992). Cell Array Width and Height Minimization. In: Layout Minimization of CMOS Cells. The Springer International Series in Engineering and Computer Science, vol 160. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3624-6_6
Download citation
DOI: https://doi.org/10.1007/978-1-4615-3624-6_6
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6611-9
Online ISBN: 978-1-4615-3624-6
eBook Packages: Springer Book Archive