Logic Block Architecture

  • Stephen D. Brown
  • Robert J. Francis
  • Jonathan Rose
  • Zvonko G. Vranesic
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 180)

Abstract

Chapter 2 described many of the commercial FPGA architectures, but provided little comment on the relative merits of each. This chapter focuses on the design of one aspect of FPGA architecture, namely the architecture of the logic blocks. We discuss the effect of the logic block design on both the total chip area needed in an FPGA to implement a given amount of logic, and the speed performance of an FPGA. The results of several studies on this topic are compared and contrasted, using a consistent notation and style of presentation.

Keywords

Expense 

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Copyright information

© Springer Science+Business Media New York 1992

Authors and Affiliations

  • Stephen D. Brown
    • 1
  • Robert J. Francis
    • 1
  • Jonathan Rose
    • 1
  • Zvonko G. Vranesic
    • 1
  1. 1.University of TorontoCanada

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