Abstract
This paper will demonstrate a method in which the high level system specification is defined using an user-friendly CASE tool together with VHSIC Hardware Description Language, VHDL. This method called SA-VHDL is especially suitable for system partitioning process of digital real-time embedded systems. A prototype tool SYS-RTA has been implemented to demonstrate the automatic conversion from the CASE tool output to the executable analysis model in VHDL. Simulation of the generated VHDL model reports the performance, i.e. response times, the resource usage, function activities and behavioural errors of the system. These results can be used for the quality analysis of the current system partitioning.
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© 1992 Springer Science+Business Media Dordrecht
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Sipola, M., Soininen, JP., Kivelä, J. (1992). Systems Real Time Analysis with VHDL Generated from Graphical SA-VHDL. In: Mermet, J. (eds) VHDL for Simulation, Synthesis and Formal Proofs of Hardware. The Kluwer International Series in Engineering and Computer Science, vol 183. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3562-1_6
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DOI: https://doi.org/10.1007/978-1-4615-3562-1_6
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