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Approaching System Level Design

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VHDL for Simulation, Synthesis and Formal Proofs of Hardware

Part of the book series: The Kluwer International Series in Engineering and Computer Science ((SECS,volume 183))

Abstract

After a definition of the term System Level, different system level design activities are identified: product specification and system level modeling, system level simulation, system level analysis and partitioning, embedding into a concurrent engineering environment. These activities then are discussed in more detail with special emphasis on modeling.

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Author information

Authors and Affiliations

  1. Universität-GH-Paderborn, FB Mathematik/Informatik, D - 4790, Paderborn, Germany

    Franz J. Rammig

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  1. Franz J. Rammig
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Editors and Affiliations

  1. Institut Méditerranéen de Technologie, Germany

    Jean Mermet

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© 1992 Springer Science+Business Media Dordrecht

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Rammig, F.J. (1992). Approaching System Level Design. In: Mermet, J. (eds) VHDL for Simulation, Synthesis and Formal Proofs of Hardware. The Kluwer International Series in Engineering and Computer Science, vol 183. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3562-1_18

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  • DOI: https://doi.org/10.1007/978-1-4615-3562-1_18

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-6582-2

  • Online ISBN: 978-1-4615-3562-1

  • eBook Packages: Springer Book Archive

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