Abstract
In this papcr we consider the problem of verifying hierarchical descriptions representing a set of interconnected synchronous Mealy finite state machines (FSM). We give a symbolic computation algorithm that builds the composite machine from the symbolic representations of the FSM components. The algorithm verifies well-formedness conditions of the resulting machine, this step detects asynchronous functional loop and bus conflicts. A tool performing this computation has been implemented and several designs has already been processed using this tool.
This research was done when the author was at BULL Research Center.
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© 1992 Springer Science+Business Media Dordrecht
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Debreil, A., Berthet, C., Jerraya, A. (1992). Symbolic Computation of Hierarchical and Interconnected FSMS. In: Mermet, J. (eds) VHDL for Simulation, Synthesis and Formal Proofs of Hardware. The Kluwer International Series in Engineering and Computer Science, vol 183. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3562-1_13
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DOI: https://doi.org/10.1007/978-1-4615-3562-1_13
Publisher Name: Springer, Boston, MA
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