Generating VHDL for Simulation and Synthesis from a High-Level DSP Design Tool
This paper describes how a commercial tool for design of digital signal processing systems at the algorithmic level has been adapted to generate VHDL that can serve as input for simulation and synthesis. Special attention will be paid to how the VHDL has to be generated in order to allow efficient synthesis using a popular commercial tool. At the same time the VHDL must be flexible so that it can provide input to other synthesis tools in the future, and generic enough to simulate on any commercial VHDL-simulator.
After a brief introduction to the background and purpose of the project, a simple design example is given as proof of concept The focus of this paper is on how VHDL is generated from the front-end DSP design tool. The following sections offer a closer look at how this VHDL is used as an interface to synthesis and simulation. A short discussion of the current limitations of the tools and possible future directions serves as the finishing point.
KeywordsRadar Sine Editing Alan
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- An introduction to the use of signal-flow block diagrams and a discussion on limited-precision effects in DSP design can be found in“Digital Signal Processing” by Alan V. Oppenheim and Ronald W. Schäfer.Google Scholar
- The book“Introduction to HDL-Based Design Using VHDL” by Steve Carlson provides exactly what the title hints. Examples in the book are prepared using the Syn-opsys synthesis tools and do not necessarily apply to other tools.Google Scholar