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Structuring Methodology

  • Jean-Michel Bergé
  • Alain Fonkoua
  • Serge Maginot
  • Jacques Rouillard

Abstract

Many different ways of structuring VHDL modeling are available to the designer. Even if, at the end of the elaboration process of the design hierarchy, all the VHDL hierarchy is translated into a set of nested blocks by the compiler, source code structuring will lead to the important properties of the description.

Keywords

Block Statement Wait Statement Configuration Mechanism Equivalent Process Design Entity 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 1992

Authors and Affiliations

  • Jean-Michel Bergé
    • 1
  • Alain Fonkoua
    • 2
  • Serge Maginot
    • 3
  • Jacques Rouillard
    • 2
  1. 1.CNETFrance
  2. 2.Institut Méditerranéen de TechnologieFrance
  3. 3.LEDA S.A.France

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