Transistor-Level Simulation for Circuit Reliability

  • Yusuf Leblebici
  • Sung-Mo (Steve) Kang
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 227)


In Chapters 2 through 4, the basic physical principles of hot-carrier induced oxide degradation in MOS transistors were discussed. Also, device models were introduced (i) to estimate the amount of damage based on operating conditions, and (ii) to predict the current-voltage characteristics of the devices after hot-carrier damage. It can be seen intuitively that in a circuit environment, the degradation of individual MOS transistors will be determined by their operating conditions within the circuit, and that this device degradation will eventually lead to circuit performance degradation. In order to account for the influence of hot-carrier effects upon circuit-level reliability, the next step will be to extend the analytical reliability estimation models developed in the previous chapters to circuit-level applications.


Circuit Simulation Interface Trap nMOS Transistor NAND Gate CMOS Inverter 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    S. Aur, D.E. Hocevar and P. Yang, “HOTRON - A circuit hot electron effect simulator,” Proc. 1987 IEEE Int. Conf. Computer-Aided Design,pp. 256–259, November 1987.Google Scholar
  2. [2]
    M.M. Kuo, K. Seki, P.M. Lee, J.Y. Choi, P.K. Ko and C. Hu, “Simulation of MOSFET lifetime under ac hot-electron stress,” IEEE Trans. Electron Devices, vol. 35, pp. 1004–1011, July 1988.CrossRefGoogle Scholar
  3. [3]
    P.M. Lee, M.M. Kuo, K. Seki, P.K. Ko and C. Hu, “Circuit aging simulator (CAS),” Proc. 1988 IEEE International Electron Devices Meeting, pp. 134–137, December 1988.Google Scholar
  4. [4]
    B.J. Sheu, W.-J. Hsu and B.W. Lee, “An integrated-circuit reliability simulator - RELY,” IEEE J. Solid-State Circuits, vol. 24, pp. 473–477, April 1989.CrossRefGoogle Scholar
  5. [5]
    L.W. Nagel, SPICE2: A computer program to simulate semiconductor circuits. Electron. Res. Lab., University of California, Berkeley, Memo. ERLM520, May 1975.Google Scholar
  6. [6]
    C. Hu, “IC reliability simulation,” IEEE J. Solid-State Circuits, vol. 27, pp. 241–246, March 1992.CrossRefGoogle Scholar
  7. [7]
    R.H. Tu, E. Rosenbaum, C.C. Li, W.Y. Chan, P.M. Lee, B.-K. Liew, J.D. Burnett, P.K. Ko and C. Hu, BERT - Berkeley Reliability Tools. Memorandum No. UCB/ERL M91/107, University of California, Berkeley, December 1991.Google Scholar
  8. [8]
    W.-J. Hsu, B.J. Sheu and S.M. Gowda, “Design of reliable VLSI circuits using simulation techniques,” IEEE J. Solid-State Circuits, vol. 26, pp. 452–457, March 1992.CrossRefGoogle Scholar
  9. [9]
    E. Takeda and N. Suzuki, “An empirical model for device degradation due to hot-carrier injection,” IEEE Electron Device Lett., vol. EDL-4, pp. 111–113, April 1983.CrossRefGoogle Scholar
  10. [10]
    C. Hu, S. Tam, F.C. Hsu, P.K. Ko, T.Y. Chan and K. W. Terrill, “Hotelectron-induced MOSFET degradation - model, monitor and improvement,” IEEE Trans. Electron Devices, vol. ED-32, pp. 375–384, February 1985.Google Scholar
  11. [11]
    R. Saleh and R. Newton, Mixed-Mode Simulation. Boston, MA: Kluwer Academic, 1990.CrossRefGoogle Scholar
  12. [12]
    Y. Leblebici and S.M. Kang, “Modeling of nMOS transistors for simulation of hot-carrier induced device and circuit degradation,” IEEE Trans. Computer-Aided Design, vol. CAD-11, pp. 235–246, February 1992.Google Scholar
  13. [13]
    Y. Leblebici and S.M. Kang, “An integrated hot-carrier degradation simulator for VLSI reliability analysis,” Proc. 1990 IEEE International Conference on Computer Aided Design, pp. 400–403, November 1990.Google Scholar
  14. [14]
    A.T. Yang and S.M. Kang, “iSMILE: A novel circuit simulation program with emphasis on new device model development,” Proc. 26th Design Automa. Conf, pp. 630–633, June 1989.Google Scholar
  15. [15]
    W. Weber, M. Brox, T. Kuenemund, H. M. Muehlhoff and D. SchmittLandsiedel, “Dynamic degradation in MOSFET’s - Part II: application in the circuit environment,” IEEE Trans. Electron Devices, vol. ED-38, pp. 1859–1867, August 1991.CrossRefGoogle Scholar
  16. [16]
    Y. Leblebici and S.M. Kang, “Simulation of MOS circuit performance degradation with emphasis in VLSI design-for-reliability,” Proc. 1989 IEEE Int. Conf. Computer Design, pp. 492–495, October 1989.Google Scholar

Copyright information

© Springer Science+Business Media New York 1993

Authors and Affiliations

  • Yusuf Leblebici
    • 1
  • Sung-Mo (Steve) Kang
    • 1
  1. 1.University of IllinoisUrbana-ChampaignUSA

Personalised recommendations