Transistor-Level Simulation for Circuit Reliability
In Chapters 2 through 4, the basic physical principles of hot-carrier induced oxide degradation in MOS transistors were discussed. Also, device models were introduced (i) to estimate the amount of damage based on operating conditions, and (ii) to predict the current-voltage characteristics of the devices after hot-carrier damage. It can be seen intuitively that in a circuit environment, the degradation of individual MOS transistors will be determined by their operating conditions within the circuit, and that this device degradation will eventually lead to circuit performance degradation. In order to account for the influence of hot-carrier effects upon circuit-level reliability, the next step will be to extend the analytical reliability estimation models developed in the previous chapters to circuit-level applications.
KeywordsCircuit Simulation Interface Trap nMOS Transistor NAND Gate CMOS Inverter
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