Abstract
Until now, the only way to “use” an entity within a design has been to declare a component, to instantiate this component, and to configure it with the given entity. Figure 5.1 illustrates these operations. The notion of a component is one of the most complicated features to be understood by the VHDL beginner. Even if this mechanism is very powerful in the general case, it can appear as very verbose in simple cases and does not improve the readability of the whole design (for designers as well as for dedicated tools). Furthermore, other HDL vendors that do not propose so sophisticated a mechanism also solve many problems and may easily claim that VHDL is too verbose.
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© 1993 Springer Science+Business Media New York
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Bergé, JM., Fonkoua, A., Maginot, S., Rouillard, J. (1993). Direct Instantiation. In: VHDL’92. The Springer International Series in Engineering and Computer Science, vol 229. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3246-0_5
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DOI: https://doi.org/10.1007/978-1-4615-3246-0_5
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