Last-Delta Activation: Postponed Process

Abstract

The concept of delta delay - simulation step seen as an infinitesimal delay - is the VHDL artifice to enforce causality in simulation. A time point of simulation consists in a variable number of delta delays that are necessary to the simulation semantics. It may happen that a designer wants to ignore what occurs during these delta delays in order to focus only on the “steady state” at the end of the time point, i.e., during the last delta.