Abstract
When the flow of control within a process or a subprogram, is being traced, it is sometimes useful to report some information to the designer. VHDL’87 proposes the assertion statement to do so:
assert FALSE report ‘I was here!’ severity NOTE;
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© 1993 Springer Science+Business Media New York
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Bergé, JM., Fonkoua, A., Maginot, S., Rouillard, J. (1993). Report Statement. In: VHDL’92. The Springer International Series in Engineering and Computer Science, vol 229. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3246-0_27
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DOI: https://doi.org/10.1007/978-1-4615-3246-0_27
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