Abstract
This chapter addresses the design of two-level pipelined processor arrays. The parallelism of algorithms is exploited both in word-level and in bit-level operations. Given an algorithm in the form of a Fortran-like nested loop program, a two-step procedure is applied. First, any word-level parallelism is exploited by using loop transformation techniques, which include a uniformization method, if required, and a decomposition of the index space into disjoint sets, which may be executed in parallel. Second, the architecture of the processing element is specified in detail by analyzing its operation at the bit level. Processors using any arithmetic system may be described. The overall design methodology is illustrated by systematically deriving a processor array for the one-dimensional (1-D) convolution algorithm. It is based on an inner product step processor that utilizes residue number system arithmetic.
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Soudris, D.J., Kyriakis-Bitzaros, E.D., Paliouras, V.R., Birbas, M.K., Stouraitis, T., Goutis, C.E. (1993). On the Design of Two-Level Pipelined Processor Arrays. In: Catthoor, F., Svensson, L. (eds) Application-Driven Architecture Synthesis. The Kluwer International Series in Engineering and Computer Science, vol 228. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3242-2_5
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DOI: https://doi.org/10.1007/978-1-4615-3242-2_5
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