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Behavioral Specification for Synthesis

  • Jos T. J. van Eijndhoven
  • Jochen Jess
  • Jens P. Brage
Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 228)

Abstract

This chapter describes some results of the Ascis project on behavioral specification languages and models used as input for high-level synthesis. Three very different languages have been investigated for input specification: Silage, HardwareC, and Vhdl. For Vhdl, a semantic and syntactic subset suitable for high-level synthesis has been chosen; an important characteristic of this subset is asynchronous communication. The specification languages are converted into a data flow graph representation. A data flow model is presented, which supports hierarchy and special control constructs for conditional and iterative statements and maximizes the opportunities for global optimizations. Standardization at this level enables a synthesis environment which supports different synthesis trajectories starting from a common entry point. Moreover, it has facilitated exchange of examples and algorithms between the project partners.

Keywords

Output Port Input Port Asynchronous Communication Hardware Description Language Behavioral Specification 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 1993

Authors and Affiliations

  • Jos T. J. van Eijndhoven
    • 1
  • Jochen Jess
    • 1
  • Jens P. Brage
    • 2
  1. 1.Dept. of Electrical EngineeringEindhoven Univ. of TechnologyMB EindhovenThe Netherlands
  2. 2.Dept. of Computer ScienceTechnical University of DenmarkLyngbyDenmark

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