The preceding three chapters have discussed the process and device effects of diodes, MOSFETs, and bipolar transistors. The underlying theme of CMOS technology was used for each of the device structures considered. In Chapter 1 we introduced several evolutionary versions of technology, including metal-gate p-well, poly-gate n-well, and twin- tub CMOS. The choice of n-well CMOS as the pedagogical example was one of convenience, owing to Stanford’s use of that technology in the early 1980s. In this chapter we consider the evolution of CMOS towards bipolar-compatible CMOS or BiCMOS technology. The possibility of developing BiCMOS is attractive because a number of performance improvements are possible. Namely, the bipolar device offers current driving, device matching, and threshold control superior to MOS. These features have led to high-speed gate arrays [7.1] and static RAMs with superior performance [7.2]. The major disadvantages of BiCMOS are increased process complexity and reduced yield due to emitter-collector shorts. In addition, the merged process can reduce performance of either the best CMOS or bipolar technology by itself. For example, by using the n-well as part of the bipolar device, the process may shift in a direction which raises the body coefficient, γ, for MOS operation (for details, see section 7.2). Conversely, constraints on epitaxial and base doping levels as imposed by the MOS devices may reduce bipolar performance — for example, lower breakdown voltage and higher output conductance (i.e. lower VA). In short, the simultaneous optimization of both bipolar and MOS devices, while at the same time trying to minimize the masking and process complexity, is a major research challenge.
KeywordsCurrent Gain Doping Profile Bipolar Device Base Doping Body Bias
Unable to display preview. Download preview PDF.
- [7.1]A. R. Alvarez, J. Teplik, D. W. Schucker, T. Hulseweh, H. B. Liang, M. Dydyk, and I. Rahim, “Second generation BiCMOS gate array technology,” Proceedings of BCTM (Bipolar Circuits and Technology Meeting) ′87, pp. 113–117, 1987.Google Scholar
- [7.2]R. A. Curtis, D. D. Smith, and T. L. Bowman, “A 12 ns 256K BiCMOS sRAM,” Digest ISSCC (Int. Solid State Circuits Conf.) ′88, pp. 186–187, 1988.Google Scholar
- [7.3]J. Miyamoto, S. Saitoh, H. Momose, H. Shibata, K. Kanzaki, and S. Kohyama, “A 1.0 μm N-well CMOS/Bipolar technology for VLSI circuits,” IEDM Technical Digest, pp. 10–13, Dec. 1983.Google Scholar
- [7.4]T.-Y. Chiu, and et. al., “Non-overlapping super self-aligned BiCMOS with 87ps low power ECL,” IEDM Technical Digest, pp.752–755, Dec. 1988.Google Scholar
- [7.5]A. R. Alvarez, ed., BiCMOS Technology and Applications. Boston: Kluwer Academic Pub., 1989.Google Scholar
- [7.6]G.W. Mclver, R.W. MiUer, T.G. O’S haughnessy, “A monolithic 16 x 16 digital multiplier,” Digest ISSCC, paper WPM6.1, pp. 54–55, 1974.Google Scholar
- [7.7]Robert Elkind, Jay Lessert, James Peterson, and Gregory Taylor, “A sub 10 nS bipolar 64 bit integer /floating point processor implemented on two circuits,” Proceedings of BCTM ′87, pp. 101–104, 1987.Google Scholar
- [7.8]Z. Yu, “Numerical model and analysis of transistors with polysilicon emitters,” Ph.D. dissertation, Stanford University, 1985.Google Scholar
- [7.9]Z. Yu, D. Chen, R. Goossens, R.W. Dutton, P.V. Voorde, and S.Y. Oh, “Accurate modeling and numerical techniques in simulation of impact-ionization effects on BJT characteristics,” IEDM Technical Digest, pp. 901–904, Dec. 1991.Google Scholar