Clock Period Constraints: Single Stage Systems
The basis for any design methodology must be a firm theoretical foundation. A designer must be able to determine, given a proposed circuit, what the limits of performance are and how design parameters affect the performance. The next two chapters of this monograph investigate the theoretical performance limits of the wave pipelining design methodology and the effect of various circuit design parameters on the circuit clock period. It will be shown that, in contrast to conventional design techniques, performance is not limited by the longest absolute delay but is instead limited by differences in delay. In addition to presenting a rigorous theoretical formulation, it is a goal of this work to present intuitive insights into how various timing parameters interact.
KeywordsInternal Node Output Register Circuit Element Combinational Logic Clock Period
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