Signal Conductors Over a Noisy Reference Plane
To obtain a high system operating frequency, both integrated circuit and multi-chip module integration levels have increased. Higher levels of integration puts stronger requirements on overall noise level for reliable operation of devices that are integrated within a system. Often in practice the worst case Simultaneous Switching Noise (SSN), and Coupled Noise (CN) are calculated independently, and these values are added to the overall noise budget calculations. With increase in device/chip integration, simple addition of worst case coupled and switching noise over-estimates their effect, and may demand a decrease in the system operating speed for reliable operation of these devices. It is essential to model the overall noise level with actual driver/receiver circuits, and using a detailed chip-package interface model. This is because the dynamic noise immunity of the input receiver not only depends on the amplitude of the noise spike but also on its pulse width [9.1]. In this chapter, a method of modeling and simulation of coupled transmission line interconnects over a noisy reference plane is presented. Limitations in using conventional coupled transmission line simulators to model signal propagation over a noisy reference plane are explained. A distributed lumped element circuit model including reference plane parasitics and associated coupling (to signal conductors) parasitics is developed, and verified using SPICE simulations.
KeywordsSignal Conductor Thin Film Technology Plane Connect CMOS Device Ground Conductor
Unable to display preview. Download preview PDF.