An investigation into the behavior of delays and SSN of CMOS devices with constant-voltage scaling was presented in Chapter 2. It appears that interconnects play a major role in the delay calculations for small geometry devices. As a result, accurate modeling of interconnect parasitics is essential for future VLSI chips. Thus detailed modeling of device and also package interconnect parasitics are required to predict the performance of the packaged small geometry CMOS devices/systems.
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