Conclusions

  • Ramesh Senthinathan
  • John L. Prince
Chapter
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 249)

Abstract

An investigation into the behavior of delays and SSN of CMOS devices with constant-voltage scaling was presented in Chapter 2. It appears that interconnects play a major role in the delay calculations for small geometry devices. As a result, accurate modeling of interconnect parasitics is essential for future VLSI chips. Thus detailed modeling of device and also package interconnect parasitics are required to predict the performance of the packaged small geometry CMOS devices/systems.

Keywords

Perforation 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Copyright information

© Springer Science+Business Media New York 1994

Authors and Affiliations

  • Ramesh Senthinathan
    • 1
  • John L. Prince
    • 2
  1. 1.Advanced Packaging Development Center (APDC)Motorola, Inc.USA
  2. 2.Center for Electronic Packaging Research (CEPR)The University of ArizonaUSA

Personalised recommendations