Delay Models and Exact Timing Analysis

Abstract

We consider anew the false path problem in timing verification. We argue that any solution to the false path problem inherently incorporates a delay model, and the answer is given in the context of this model. We make explicit the delay model underlying both the “floating” and “transition” sensitization computations, and give the basic assumption underying gate sensitization. We extend sensitization 88theory for the delay model underlying the ”floating mode“ computation to general (complex, possibly asymmetric) gates. This leads to the ability to compute the exact delay of a circuit under the given delay model. We give a new delay model and sensitization computation for ”transition mode“ under a bounded delay model and show that for every bounded delay model there is a natural time quantum such that on each integer-multiple bounded interval of the quantum every signal is a constant. Algorithms for exact delay computation for both floating mode and transition mode delay are given. An implementation for the floating mode model yields practical results on large benchmark circuits.