Abstract
Logic synthesizer, the Transduction method, was developed in the early 1970s at the University of Illinois, but its usefulness has been only recently recognized in the industry. The original Transduction method handles only NOR gates, though it is still useful for the design of ECL networks. So, since then, SYLON has been developed as its extension, focusing on the design of CMOS circuits. Currently SYLON has three programs, i.e., XTRANS, DREAM, and REDUCE. Each has its own unique features. The basic concepts of the Transduction method and SYLON are discussed along with recent results.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Bohm, M. A., and Gregory, D., “Production Applications for Logic Synthesis and Optimization”, VLSI System Design, Jan. 1988, pp. 40–43.
Bostick, D., Hachtel G. D., Jacoby, R., Lightner, M. R., Moceyunas, P., Morrison, C. R., and Ravenscroft, D., “The Boulder Optimal Logic Design System”, Proc. ICCAD, 1987, pp. 62–65.
Brayton, R. K., Rudell, R., Sangiovanni-Vincentelli, A. and Wang, A. R., “MIS: A multiple-level Logic Optimization”, IEEE TCAD, 6, Nov. 1987, pp. 1062–1081.
Chen, K. C. and Muroga, S., “SYLON-DREAM: A Multi-Level Network Synthesizer”, Proc. ICCAD, 1989, pp. 552–555.
Chen, K. C. and Muroga, S., “Timing Optimization for Multi-Level Combinational Networks”, Proc. DAC, 1990, pp. 339–344.
Chen, K. C., “Logic Synthesis and Optimization Algorithms”, Ph. D. Thesis, Dept. of Computer Science, Univ. of Illinois at Urbana-Champaign, 1990.
de Geus, A. J. and Cohen, W., “A Rule-Based System for Optimizing Combinational Logic”, IEEE DesigneTest, Aug. 1985, pp. 22–32.
Gregory, D., Bartlett, K., de Geus, A., and Hachtel, G., “SOCRATES: A System for Automatically Synthesizing and Optimizing Combinational Logic”, Proc. DAC, 1986, pp. 79–85.
Hachtel G., Jacoby, R., and Moceyunas, C., “On Computing and Approximating the Observability Don’t-Care Set”, Int. Workshop on Logic Synthesis, Research Triangle Park, NC, May 1989.
Hu, J. K. C., “Logic Design Methods for Irredundant MOS Networks”, Ph. D. Thesis, Dept. of Computer Science, Univ. of Illinois at Urbana-Champaign, 1978.
Ibaraki, T., and Muroga, S., “Synthesis of Networks with a Minimum Number of Negative Gates”, Dept. Comput. Sci., Univ. of Ill. at Urbana-Champaign, Rep. no. 309, Feb. 1969, 46 pp. Also IEEE TC, vol. C-20, no. 1, Jan. 1971, pp. 49–58.
Ibaraki, T., “Gate-interconnection Minimization of Switching Networks Using Negative Gates”, IEEE TC, C-20, no. 6, June 1971, pp. 698–706.
Kambayashi, Y., and Muroga, S., “Network Transduction Based on Permissible Functions (General Principles of NOR Network Transduction NETTRA Programs)”, UIUCDCS-R-76–804, Dept. Comp. Sci., Urbana, Ill., June 1976.
Lai, H. C. and Muroga, S., “Automated Logic Design of MOS Networks”, Chap. 5, Adv. Inf. Sys. Sci., vol. 9, ed. J. Tou, Plenum Publishing Co., 1985, pp. 187–336.
Lai, H. C. and Muroga, S., “Design of MOS Networks in Single-Rail Input Logic for Incompletely-Specified Functions”, IEEE TCAD, vol. 7, March 1988, pp. 339–345.
Limqueco, J. C., “Logic Optimization of MOS Networks”, Ph. D. Thesis, Department of Computer Science, University of Illinois at Urbana-Champaign, 1992, 250 pp.
Limqueco, J. C., “Algorithms for the Design of Irredundant MOS Networks”, M. S. Thesis, Department of Computer Science, University of Illinois at Urbana-Champaign, 1988, 87 pp.
Limqueco, J. C. and Muroga, S., “SYLON-REDUCE: A MOS Network Optimization Algorithm Using Permissible Functions”, Proc. ICCD, 1990, pp. 282–285.
Limqueco, J. C. and Muroga, S., “Logic Optimization of MOS Networks”, Proc. DAC, 1991, pp. 464–469.
] Limqueco, J. C. and Muroga, S., “Timing Optimization of MOS Combinational Networks”, Proc. Int. ASIC Conf., 1991, P-13.
Limqueco, J. C., and Muroga, S., “Optimizing Large Networks by Repeated Local Optimization”, ISCAS, May 1992
Lisanke, R. “Logic synthesis and optimization benchmarks user guide, version 2.0”, Tech. Rep., Microelectronics Center of North Carolina, Research Triangle Park, N. C., Dec. 16, 1988, 61 pages. Distributed at International Workshop on Logic Synthesis, May 1989.
Liu, T. K., “Synthesis of Logic Networks with MOS Complex Cells”, Ph. D. Thesis, Report No. UIUCDCS-R-72–517, Department of Computer Science, University of Illinois at Urbana-Champaign, 1972.
Liu, T. K. “Synthesis algorithms for 2-Level MOS networks”, IEEE TC, C-24, no. 1, Jan. 1975, pp. 72–79.
Liu,T. K., “Synthesis of Multilevel Feed-Forward MOS Networks”, IEEE TC, Vol. C-26, June 1977, pp. 581–588.
Liu,T. K., “Synthesis of Feed-Forward MOS Networks with Cells of Similar Complexities”, IEEE TC, Vol. C-26, Aug. 1977, pp. 826–831.
McGeer, P. C. and Brayton, R. K., “The Observability Don’t-Care Set and Its Approximations”, Proc. ICCD, 1990, pp. 45–48.
Muroga, S., “Computer-aided Logic Synthesis for VLSI Chips”, in Advances in Computers, vol. 32, ed. by M. Yovits, Academic Press, 1991, pp. 1–103.
Muroga, S., Kambayashi, Y., Lai, H. C., and Culliney, J. N., “The Transduction Method — Design of Logic Networks Based on Permissible Functions”, IEEE TC, Oct. 1989, pp. 1404–1424.
Muroga, S., Xiang, X. Q., Limqueco, J., Lin, L. P., and Chen, K. C., “A Logic Network Synthesis System, SYLON”, Proc. ICCD, 1989, pp. 324–328.
Nakamura, K., “Synthesis of gate minimum multioutput two-level negative-gate networks”, IEEE TC, C-28, Oct. 1979, pp. 768–772.
Nakamura, K., Tokura, N., and Kasami, T., “Minimal Negative-gate Networks”, IEEE TC, Vol. C-21, Jan. 1972, pp. 5–11.
Savoj, H. and Brayton, R. K., “The Use of Observability and External Don’t Cares for the Simplification of Multi-Level Networks”, Proc. DAC, 1990, pp. 297–301.
Su, Y. H., and Nam, C. W., “Computer-aided Synthesis of Multiple-output Multi-level NAND Networks with Fan-in and Fan-out Constraints”, IEEE Trans. Comput., C-20, Dec. 1971, pp. 445–1455.
Xiang, X., “Multilevel Logic Network Synthesis System, SYLON-XTRANS and Read-Only Memory Minimization Procedure, MINROM”, Ph. D.Thesis, Dept. of Computer Science, Univ. of Illinois at Urbana-Champaign, 1990.
Xiang, X. and Muroga, S., “Synthesis of Multilevel Networks with Simple Gates”, Int. Workshop on Logic Synthesis, Research Triangle Park, NC, May 1989.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1993 Springer Science+Business Media New York
About this chapter
Cite this chapter
Muroga, S. (1993). Logic Synthesizers, The Transduction Method and Its Extension, Sylon. In: Sasao, T. (eds) Logic Synthesis and Optimization. The Kluwer International Series in Engineering and Computer Science, vol 212. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3154-8_3
Download citation
DOI: https://doi.org/10.1007/978-1-4615-3154-8_3
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6381-1
Online ISBN: 978-1-4615-3154-8
eBook Packages: Springer Book Archive