Abstract
Asynchronous or self-timed systems that do not rely on a global clock to keep system components synchronized can offer significant advantages over traditional clocked circuits in a variety of applications. However, design of self-timed systems has long been considered too difficult because of the specialized circuits required and the lack of tools available to help the designer explore the potential of such systems. This article describes one approach to ease the design and implementation of self-timed systems that involves compiling concurrent process descriptions directly into self-timed circuits.
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Sponsored in part by NSF grant MIP-9111793.
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References
C.L. Seitz, “System timing,” in Mead and Conway, eds., Introduction to VLSI Systems, Reading, MA: Addison-Wesley, 1980, chap. 7.
E. Brunvand, “Translating concurrent communicating programs into asynchronous circuits,” Ph.D. thesis, Carnegie Mellon University, 1991. Available as Technical Report CMU-CS-91-198.
I. Sutherland, “Micropipelines” Communications of the ACM, vol. 32, 1989, pp. 720–738.
A.J. Martin, “Compiling communicating processes into delay insensitive circuits,” Distributed Computing, vol. 1, 1986.
S. Burns, “Automated compilation of concurrent programs into self-timed circuits,” Master’s thesis, Caltech, 1987.
C. Niessen, C.K. van Berkel, M. Rem, and R.W. Saeijs, “VLSI programming and silicon compilation; a novel approach from Philips research,” in ICCD, (Rye Brook, NY), October 1988.
T.H.-Y. Meng, R.W. Broderson, and D.G. Messerschmitt, “Design of clock-free asynchronous systems for real-time signal processing,” in ICASSP-89, IEEE, May 1989, pp. 2532–2535.
J.C. Ebergen, “Translating programs into delay-insensitive circuits,” Ph.D. thesis, Technische Universiteit Eindhoven, 1987.
Inmos, Occam Programming Manual, 1983.
E. Brunvand and M. Starkey, “An integrated environment for the design and simulation of self-timed systems,” in VLSI-91, IFIP, August 1991.
E. Brunvand, N. Michell, and K. Smith, “A comparison of self-timed design using FPGA, CMOS, and GaAs technologies,” to appear in ICCD’92.
J.T. Udding, “A formal model for defining and classifying delay-insensitive circuits and systems,” Distributed Computing, vol. 1, 1986, pp. 197–204.
E. Brunvand, “Parts-R-Us: A chip aparts …” Tech. Rep. CMU-CS-87-119, Carnegie Mellon University, 1987.
I.E. Sutherland, R.F. Sproull, and I. Jones, “iStandard asynchronous modules,” Technical Memo 4662, Sutherland, Sproull and Associates, 1986.
E. Brunvand, “A cell set for self-timed design using actel FPGAs” Technical Report UUCS-91-013, University of Utah, 1991.
E. Brunvand, “Implementing self-timed systems with FPGAs,” in FPGAs, W.R. Moore and W. Luk, eds., Abingdon EE&CS Books, 1991, chap. 6.2, pp. 312–323.
A.J. Martin, “The limitation of delay-insensitivity in asynchronous circuits,” in Advanced Research in VLSI, MIT Press, 1990.
W.A. Clark, “Macromodular computer systems,” in Spring Joint Computer Conference, AFIPS, April 1967.
S.M. Orenstein, M.J. Stucki, and W.A. Clark, “A functional description of macromodules,” in Spring Joint Computer Conference, AFIPS, 1967.
C.A.R. Hoare, Communicating Sequential Processes, Englewood Cliffs, NJ: Prentice-Hall, 1985.
M. Starkey, “A LISP based OCCAM interpreter,” Technical Report UUCS-91-002, Computer Science Department, University of Utah, 1990.
A.J. Martin, “The probe: an addition to communication primitives,” Information Processing Letters, vol. 20, 1985.
T.J. Chaney and C.E. Molnar, “Anomalous behavior of synchronizer and arbiter circuits,” IEEE Transactions on Computers, vol. C-22, 1973, pp. 421–422.
C.L. Seitz, “Ideas about arbiters,” Lambda, First Quarter 1980, pp. 10–14.
F.U. Rosenberger, C.E. Molnar, T.J. Chaney, and T.-P. Fang, “Q-modules: internally clocked delay-insensitive modules,” IEEE Transactions on Computers, vol. 37, 1988.
D.L. Dill, Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits. MIT Press, 1989. An ACM Distinguished Dissertation.
N. Michell, “GaAs PPL cell set,” Technical Report UUCS-91-015, University of Utah, 1991.
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Brunvand, E. (1994). Designing Self-Timed Systems Using Concurrent Programs. In: Meng, T.H., Malik, S. (eds) Asynchronous Circuit Design for VLSI Signal Processing. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2794-7_5
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DOI: https://doi.org/10.1007/978-1-4615-2794-7_5
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