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Geometry Sharing Placement

  • John M. Cohn
  • David J. Garrod
  • Rob A. Rutenbar
  • L. Richard Carley
Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 263)

Abstract

The ability to arrange devices such that critical structures are shared between several devices is the layout designer’s most powerful tool for the reduction of layout induced parasitics and the improvement of layout density. This chapter introduces unique features which allow us to optimize dynamically such geometry sharing during placement1. These features have been added as a functional layer on top of the topologically-constrained placement function described in Chapters 2.0 and 3.0.

Keywords

Parasitic Capacitance Device Generation Device Terminal Substrate Contact Area Saving 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Notes

  1. 1.
    Note: we refer to such geometry sharing optimizations as device merging or simply merging as a convenient shorthand.Google Scholar
  2. 2.
    For example, the MOSIS 2um pwell CMOS fabrication process, p-diffusion has 16X more capacitance/area than metali.Google Scholar
  3. 3.
    In certain circumstances, however, device geometry sharing can make some device terminals more difficult to reach[18], putting a larger burden on the router.Google Scholar
  4. 4.
    The algorithm assumes that rectilinear terminal geometry can be fractured into nonoverlapping rectangular regions.Google Scholar
  5. 5.
    The exception being silicon-on-insulator processes.Google Scholar
  6. 6.
    The procedure for n-well process is essentially identical.Google Scholar

Copyright information

© Springer Science+Business Media New York 1994

Authors and Affiliations

  • John M. Cohn
    • 1
  • David J. Garrod
    • 1
  • Rob A. Rutenbar
    • 1
  • L. Richard Carley
    • 1
  1. 1.Carnegie Mellon UniversityUSA

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