Abstract
Analog circuit performance is often determined by the degree to which device characteristics and interconnect parasitics can be made to match. This chapter introduces a set of topological placement constraints aimed at improving analog performance through better device matching and symmetric parasitic matching. These features, which are added as a functional layer on top of the basic placement function described in Chapter 2.0, are the first which tailor KOAN specifically to analog layout.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Notes
A similar model describing the behavior of passive components is given in [14].
For this technique to be effective, however, this same thermal symmetry about a line which bisects the substrate must be observed throughout the layout of the entire chip.
Note, the source and drain can be swapped at the designers option.
The device-center constraint can also be used in conjunction with all the other constraints to create mixed asymmetric-symmetric perfectly-symmetric placements if matching requirements dictate.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 1994 Springer Science+Business Media New York
About this chapter
Cite this chapter
Cohn, J.M., Garrod, D.J., Rutenbar, R.A., Carley, L.R. (1994). Topological Placement. In: Analog Device-Level Layout Automation. The Kluwer International Series in Engineering and Computer Science, vol 263. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2756-5_3
Download citation
DOI: https://doi.org/10.1007/978-1-4615-2756-5_3
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6189-3
Online ISBN: 978-1-4615-2756-5
eBook Packages: Springer Book Archive